Transcript ppt
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 25: November 7, 2011 Registers 1 Penn ESE370 Fall2011 -- Mehta & DeHon Previously… Clocking Discipline • Follow discipline of combinational logic broken by registers • Compute – From state elements – Through combinational logic – To new values for state elements • As long as clock cycle long enough, – Will get correct behavior 2 Penn ESE370 Fall2011 -- Mehta & DeHon Today • Clocking: Register Designs – Dynamic – Static 3 Penn ESE370 Fall2011 -- Mehta & DeHon Gate-Latch-Register • • • • Transistor Count? Total Transistor Width? Capacitive load on data input? Capacitive load on clock? 4 Penn ESE370 Fall2011 -- Mehta & DeHon Alternate Registers 5 Penn ESE370 Fall2011 -- Mehta & DeHon How does this work as a register? 6 Penn ESE370 Fall2011 -- Mehta & DeHon Compare Gate-Latch-Register • • • • Transistor Count? Total Transistor Width? Load on input? Load on Clock(s)? 7 Penn ESE370 Fall2011 -- Mehta & DeHon Weaknesses? 8 Penn ESE370 Fall2011 -- Mehta & DeHon Weaknesses • Hold value on capacitance (“Dynamic”) – Not actively driven • Easily upset by noise – Will leak away eventually • Sets lower bound on clock frequency • Cannot “gate off” clock when not in use • Not drive to rail – Less noise margin – More static leakage – PMOS not completely off Penn ESE370 Fall2011 -- Mehta & DeHon 9 How Improve? • Remember weaknesses: – Holds value dynamically – Not driven to rail 10 Penn ESE370 Fall2011 -- Mehta & DeHon What is the difference? 11 Penn ESE370 Fall2011 -- Mehta & DeHon Transmission Gates • Idea: use both NMOS/PMOS in parallel – NMOS passes the strong 0 – PMOS passes the strong 1 – Pass gates that swing full rail • Often used in mux 12 Penn ESE370 Fall2011 -- Mehta & DeHon Transmission Gate Mux S S 1 In1 In2 /S /S 2 S How is this different from a static mux? 13 Penn ESE370 Fall2011 -- Mehta & DeHon How Improve? • Remember weaknesses: – Holds value dynamically – Not driven to rail 14 Penn ESE370 Fall2011 -- Mehta & DeHon Level Restorer (“Staticizer”) 15 Penn ESE370 Fall2010 -- DeHon Without level restorer 16 Penn ESE370 Fall2010 -- DeHon With level restorer 17 Penn ESE370 Fall2010 -- DeHon Level Restore • What issue arises here? 18 Penn ESE370 Fall2010 -- DeHon Level Restore • What issue arises here? 19 Penn ESE370 Fall2010 -- DeHon Register with Level Restore 20 Penn ESE370 Fall2011 -- Mehta & DeHon Static Register 21 Penn ESE370 Fall2011 -- Mehta & DeHon Static Register • • • • Transistors? Total width? Clock load? Input load? 22 Penn ESE370 Fall2011 -- Mehta & DeHon Comparison Gate Latch Dynamic Latch Static Latch Area Large Small Moderate Input Cap Small Moderate Moderate Delay Slow Fast Fast Dynamic No Yes No Full Rail Yes No Yes 23 Penn ESE370 Fall2011 -- Mehta & DeHon Typical Static Register Advantages: • Static • Full Rail • Fast Isolation inverters: • Input Cap • Input/Output Noise • State Node Noise Phi0 /Phi0 24 Penn ESE370 Fall2011 -- Mehta & DeHon Admin • Midterm Review tonight at 8pm (Moore 204) • Tuesday: Andre away (no office hour) • Wednesday: Midterm – No lecture – Midterm 7-9pm in Towne 303 – New Project out • Thursday: <nothing> (read project) • Friday: Class (Andre) 25 Penn ESE370 Fall2011 -- Mehta & DeHon Ideas • Registers can be implemented more compactly with pass transistor-based designs 26 Penn ESE370 Fall2011 -- Mehta & DeHon