Transcript ppt

ESE370:
Circuit-Level
Modeling, Design, and Optimization
for Digital Systems
Day 26: November 10, 2010
Memory Periphery
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Today
• Decode
• Sensing
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Memory Bank
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Row Select
• Logically a big AND
– May include an enable for timing in
synchronous
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Row Select
• How can we do better?
– Area
– Delay
– Match to pitch of
memory row
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Row Select
• Compute inversions outside array
– Just AND appropriate line (bit or /bit)
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Row Select
• Share common terms
• Multi-level decode
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Row Select
• Same number of lines
• Half as many AND inputs
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Row Select: Precharge NAND
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Sensing
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Differential Sense Amp
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Differential Sense Amp
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“Inverter”
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“Inverter”
• Input high
– Ratioed like
grounded P
• Input low
– Pulls itself up
– Until Vdd-VTP
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DC Transfer Function
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Differential Sense Amp
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Differential Sense Amp
• “Inverter” output
controls PMOS for
second inverter
• Sets PMOS
operating point
– current
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Differential Sense Amp
• View:
– Current mirror
– Biases where
inverter operating
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Differential Sense Amp
• View:
– adjusting the pullup
load resistance
– Changing the trip
point for “inverter”
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DC Transfer /in with in=0.5V
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DC Transfer Various in
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After Inverter
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Connect to Column
• Equalize lines during precharge
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Singled-Ended Read
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5T SRAM
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Single Ended
• Need reference to compare against
• Want to look just like bit line
• Equalize with bit line
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Split Bit Line
• Split bit-line in half
• Precharge/equalize both
• Word in only one half
– Only it switches
• Amplify difference
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Open Bit Line Architecture
• For 1T DRAM
• Add dummy cells
• Charge dummy cells to
Vdd/2
• “read” dummy in
reference half
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Memory Bank
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Admin
• Have memory cell
– Add drivers and amps
• Andrew office hours Wednesday and
Thursday
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Idea
• Minimize area of repeated cell
• Compensate with periphery
– Amplification (restoration)
• Match periphery pitch to cell row/column
– Decode
– Sensing
– Writer Drivers
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