Transcript ppt
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 25: November 8, 2010 Memory Core 1 Penn ESE370 Fall2010 -- DeHon Today • 6T SRAM review • 5T SRAM – Charge sharing – Precharge • Multiport SRAM • DRAM • Leakage 2 Penn ESE370 Fall2010 -- DeHon Memory Bank 3 Penn ESE370 Fall2010 -- DeHon SRAM Memory bit 4 Penn ESE534 Spring2010 -- DeHon Memory Bank 5 Penn ESE370 Fall2010 -- DeHon 5T SRAM 6 Penn ESE370 Fall2010 -- DeHon Consider • What happens to voltage at A when WL turns from 01 – Assume Waccess large – Waccess >> Wpu=1 7 Penn ESE370 Fall2010 -- DeHon Voltage After enable Word Line • • • • QBL = 0 QA = (1V)(g(2+Waccess)C0) CBL>>CA=(g(2+Waccess)C0) After enable Waccess – Total charge roughly unchanged – Distributed over larger capacitance~=CBL – VA=VBL~= CA/CBL 8 Penn ESE370 Fall2010 -- DeHon Larger Resistance? • What happens if Waccess small? – Waccess < Wpu 9 Penn ESE370 Fall2010 -- DeHon Simulation: Waccess=100 10 Penn ESE370 Fall2010 -- DeHon Simulation 11 Penn ESE370 Fall2010 -- DeHon Charge Sharing • Charge sharing can pull down voltage 12 Penn ESE370 Fall2010 -- DeHon Consider • What happens to voltage at A when WL turns from 01 – Assume Waccess large 13 Penn ESE370 Fall2010 -- DeHon Simulation Waccess=20 14 Penn ESE370 Fall2010 -- DeHon Simulation Waccess=4 15 Penn ESE370 Fall2010 -- DeHon Charge Sharing • Charge sharing can lead to read upset – Charge redistribution adequate to flip state of bit 16 Penn ESE370 Fall2010 -- DeHon How might we avoid? 17 Penn ESE370 Fall2010 -- DeHon Precharge to middle Voltage • Precharge to Vdd/2 • Now charge sharing doesn’t swing to opposite side of midpoint 18 Penn ESE370 Fall2010 -- DeHon Simulation Waccess=20 19 Penn ESE370 Fall2010 -- DeHon Multiport RAM 20 Penn ESE370 Fall2010 -- DeHon Mulitport • Perform multiple operations simultaneously – E.g. Processor register file • R3R1+R2 • Requires two reads and one write 21 Penn ESE370 Fall2010 -- DeHon Simple Idea • Add access transistors 22 Penn ESE370 Fall2010 -- DeHon Watch? • What do we need to be careful about? 23 Penn ESE370 Fall2010 -- DeHon Isolate BL form Mem Larger, but more robust Essential for large # of read ports 24 Penn ESE370 Fall2010 -- DeHon Adding Write Port 25 Penn ESE370 Fall2010 -- DeHon Write Port • What options does this raise? 26 Penn ESE370 Fall2010 -- DeHon Opportunity • Asymmetric cell size • Separate sizing constraints – Weak drive into write port (Wrestore) – Strong drive into read port (Wbuf) 27 Penn ESE370 Fall2010 -- DeHon Multiple Write Ports 28 Penn ESE370 Fall2010 -- DeHon DRAM 29 Penn ESE370 Fall2010 -- DeHon 1T 1C DRAM • Simplest case – Memory is capacitor – Feature of DRAM process is ability to make large capacitor compactly 30 Penn ESE370 Fall2010 -- DeHon 1T DRAM • What happens when read this cell? 31 Penn ESE370 Fall2010 -- DeHon 1T DRAM • On read, charge sharing – VBL = (Cbit/CBL)Vstore • Small swing on bit line – Must sense – Means want large Cbit – Limits bits/bitline so VBL large enough • Cell always depleted on read – Must be rewritten 32 Penn ESE370 Fall2010 -- DeHon Dynamic RAM • Takes sharing idea one step further • Share refresh/restoration logic as well 33 Penn ESE534 Spring2010 -- DeHon 3T DRAM 34 Penn ESE370 Fall2010 -- DeHon 3T DRAM • How does this work? 35 Penn ESE370 Fall2010 -- DeHon 3T DRAM • Correct operation not sensitive to sizing • Does not deplete cell on read • No charge sharing with stored state • Must use Vdd+VTN on BL to write full voltage Penn ESE370 Fall2010 -- DeHon 36 Some Numbers (memory) • Register as stand-alone element 4Kl2 • Static RAM cell 1Kl2 – SRAM Memory (single ported) • Dynamic RAM cell (DRAM process) 100l2 • Dynamic RAM cell (SRAM process) 300l2 37 Penn ESE534 Spring2010 -- DeHon Energy 38 Penn ESE370 Fall2010 -- DeHon Single Port Memory • What are most cells doing on a cycle? • What fraction is involved in a read/write? – When not doing a read or write? • Reads are slow – Cycles long lots of time to leak 39 Penn ESE370 Fall2010 -- DeHon ITRS 2009 45nm Low Power Isd,leak Isd,sat High Performance 100nA/mm 1200 mA/mm Cg,total Vth 1fF/mm 285mV 0.91fF/mm 585mV 50pA/mm 560mA/mm C0 = 0.045mm × Cg,total 40 Penn ESE370 Fall2010 -- DeHon High Power • V=1V d=1000 g=0.5 • Full swing for simplicity • Csc = 0 – (just for simplicity, typically <Cload) • Cload=1000C0 ≈ 45 fF = 45×10-15F • WN = 2 Ileak = 9×10-9 A • P= (45×10-15) freq + 1000×9×10-9 W 41 Penn ESE370 Fall2010 -- DeHon Relative Power • P= (45×10-15) freq + 1000×9×10-9 W • P= (4.5×10-14) freq + 9×10-6 W • Break even at freq=200MHz • Partial swing on bit line Reduce dynamic energy Increase percentage in leakage energy 42 Penn ESE370 Fall2010 -- DeHon Consequence • Leakage energy can dominate in large memories • Care about low operating (or stand-by) power • Use process with high Vth – Reduce leakage at expense of speed 43 Penn ESE370 Fall2010 -- DeHon Admin • Size your memory cell • André office hours Tuesday • Andrew office hours Wednesday and Thursday 44 Penn ESE370 Fall2010 -- DeHon Idea • Memory can be compact • Rich design space • Demands careful sizing 45 Penn ESE370 Fall2010 -- DeHon