Transcript ppt

ESE370:
Circuit-Level
Modeling, Design, and Optimization
for Digital Systems
Day 7: September 22, 2010
Delay and RC Response
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Delay is RC Charging
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Delay is RC Charging
• Understand switch
state
• Break into stages
• For each stage
– Understand Rdrive
– Understand Cload
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Today
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RC Charging
RC Step Response
What is the C?
What is the R?
Measuring Delay
Delay model of gate
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90% Rise Time?
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What does response look like?
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What does look like?
V (t)  1  e
t /(RC )
V
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Shape of Curve
x
e-x
1-e-x
0
0.1
1
2
2.3
V (t)  1  e
Penn ESE370 Fall2010 -- DeHon
t /(RC )
V
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Shape of Curve
x
e-x
1-e-x
0
0.1
1
2
2.3
1
0.9
1/e = 0.37
1/e2 = 0.14
0.1
0
0.1
0.66
0.86
0.9
V (t)  1  e
Penn ESE370 Fall2010 -- DeHon
t /(RC )
V
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What is C?
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Capacitance
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•
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•
Wire
MOSFET gate
Logical Gate
Fanout -- Total gate load
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Wire Capacitance
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Wire Capacitance
A
C   r 0
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There are always Rs and Cs
• Modeling vs. discrete components
• Dominant effects
– Rbig + Rsmall ≈ Rbig
– Cbig || Csmall ≈ Cbig
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First Order Model
• Switch
– Loads input capacitively
• As dig in, understand:
– Origin of capacitance
– How can we engineer
– Tradeoffs
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Logic Gate Input Capacitance
• Capacitance on
– A input?
– B input?
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Fanout in Circuit
• Output routed to many gate inputs
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Fanout in Circuit
• Maximum fanout?
• Second?
• Min?
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Lumped Capacitive Load
Cload 
C
gi
i fanout

C
wi
iwires
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What is R?
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Resistance
• Wire resistance
– Supply to transistor source
– Transistor output gate it is driving
• Transistor equivalent resistance
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Wire Resistances
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First Order Model
• Switch
– Resistive driver
• As dig in, understand:
– More sophisticated view
– How can we engineer
– Tradeoffs
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Equivalent Resistance
• What resistances might transistors
contribute?
– How many cases?
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Lumped Resistive Source
Rdrive  Rtrnet 
R
wi
 R pwr
iwires
Rtrnet = parallel and series combination of Rtr
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Measuring Delay
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Measuring Gate Delay
• Next stage starts to switch before first
finishes
• Measure
50%--50%
67ps
80ps
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Characterizing Gate/Technology
• Delay measure will be
– Function of load on gate
– Function of input rise time
• Which, in turn, may be a function of input
loading
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Delay vs. Risetime
1ps rise
10ps delay
100ps rise
20ps delay
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Characterizing Gate/Technology
• Delay measure will be
– Function of load on gate
– Function of input rise time
• Which, in turn, may be a function of input
loading
• Want to understand typical
– At least comparable
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Measuring/Characterizing
• Drive with a gate
– Not an ideal source
• Measure loaded gate
– Typical loading – FO4
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HW2 Recommendation
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Rise/Fall
• Rise and Fall time may differ
– Why?
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Delay Model of Gate
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Sample Gate
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Sample Gate
• Internal stages
have delay
• External depend on
load
• Assume
(guarantee) all
inputs same load
t gate  A  B  fanout
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Sample Gate
• What is A?
• B?
t gate  A  B  fanout
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Admin
• HW1 grades posted
• HW2 due Friday
• Here on Friday for lecture
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Delay is RC Charging
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