Transcript ppt

ESE370:
Circuit-Level
Modeling, Design, and Optimization
for Digital Systems
Day 2: September 10, 2010
Transistor Introduction
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Penn ESE370 Fall2010 -- DeHon
Today
• MOSFET
• Capacitive and resistive loads
• Simplified models
– Zero-th order model
• Good enough for ???
– First order model
• There are always Rs and Cs
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MOSFET
• Metal Oxide Semiconductor Field Effect
Transistor
– New device
– Primary active component for the term
– Three terminal device
• Voltage at gate controls conduction between
two other terminals (source, drain)
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MOSFET I vs. Vgs, Vds
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MOSFET I vs. Vgs, Vds
• Will dig into
understanding
during term
• Today simple ways
to reason about
gross behavior
– Static/DC
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Preclass
• What voltage do the cases converge to?
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Conclude?
• DC/Steady-State
– Ignore the capacitors
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Quasistatic
• Static – inputs (and circuit) unchanging,
how does it settle?
• Dynamic – what happens when things
change
• Quasi-Static – inputs transition, circuit
responds, and settles
– Dynamic transition to roughly static states
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Quasistatic Relevance?
• How relevant to a combinational digital
circuit?
• How relevant to a clocked digital circuit?
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Zero-th Order MOSFET
• Ideal Switch
Vgs > Vth  conducts
Vgs < Vth  does not conduct
Vth – threshold voltage
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Zero-th Order MOSFET
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N-Type, P-Type
• N – negative
carriers
– electrons
• Switch turned on
positive Vgs
• P – positive carriers
– holes
• Switch turned on
negative Vgs
Vth<0
Vgs<Vth to
to conduct
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Why useful?
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What happens when
Vin=Vdd>Vth
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What happens when
Vin=Vdd>Vth
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Vgs=Vdd > Vth
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What happens when
Vin=Vdd>Vth
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Vgs=Vdd > Vth
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What happens when
Vin=Vdd>Vth
Vgs=0 > Vth
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Vgs=Vdd > Vth
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What happens when
Vin=Vdd>Vth
Vgs=0 > Vth
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Vgs=Vdd > Vth
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What happens when
Vin=Vdd>Vth
Vgs=0 > Vth
V2=Gnd
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Vgs=Vdd > Vth
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What happens when
Vin=Vdd>Vth
Vgs=0 > Vth
V2=Gnd
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Vgs=Vdd > Vth
Vgs=0 < Vth
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What happens when
Vin=Vdd>Vth
Vgs=0 > Vth
V2=Gnd
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Vgs=Vdd > Vth
Vgs=0 < Vth
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What happens when
Vin=Vdd>Vth
Vgs=0 > Vth
V2=Gnd
Penn ESE370 Fall2010 -- DeHon
Vgs=Vdd > Vth
Vgs=0 < Vth
Vout=Vdd
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What happens when
Vin=0<Vth
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What happens when
Vin=0<Vth
V2=Vdd
Vout=0
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What function?
Buffer
• Vin=Vdd  Vout=Vdd
• Vin=0  Vout=0
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Why Useful?
• Allows us to reason (mostly) at logic
level about steady-state functionality of
typical gate circuits
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Why adequate?
• Static analysis – can ignore capacitors
• Capacitive loads – resistances don’t matter
• Feed forward for gates –
– don’t generally have loops
– can work forward from known values
• Logic drive rail-to-rail
– Don’t have to reason about intermediate voltage
levels
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What not tell us?
• Delay
• Dynamics
• Behavior if not
– Capacitively loaded
– Loops
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First Order Model
• Switch
– Loads input capacitively
– Has finite drive strength
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First Order Model
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First Order Model
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Refine to First Order
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Zero-th Order Tells us how
switches set (Vin=0)
V2=Vdd
Vout=0
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Zero-th Order Tells us how
switches set (Vin=0)
V2=Vdd
Vout=0
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Zero-th Order Tells us how
switches set (Vin=0)
• Leaves an RC Circuit we can analyze
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Zero-th Order Tells us how
switches set (Vin=0)
• Look at middle stage
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What more this tell us?
• Delay
• Quastistatic behavior
• Voltage settling with resistive loads
– At least some basis for reasoning
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What is this leaving out?
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What is this leaving out?
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What leaving out?
• What happens at intermediate voltages
– Not rail-to-rail
• Details of dynamics, including…
– Input not transition as step
– Intermediate drive strengths change with
Vgs
– As output charges Vds changes, changing
drive strenght
• Isn’t really 0 current below threshold
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Engineering Control
• Vth – process engineer
• Drive strength – circuit engineer control
with sizing
• Supply voltages – range set by process,
detail use by circuit design
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Engineering Control:
Threshold
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Engineering Control:
Drive Strength
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Wire Capacitance
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Wire Capacitance
A
C   r 0
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Wire Resistance
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Wire Resistance
R
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L
A
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Wire Resistance
• Sanity check
– Wire twice as long = resistors in series
– Wire twice as wide = resistors in parallel
R
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L
A
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There are always Rs and Cs
• Modeling vs. discrete components
• Dominant effects
– Rbig + Rsmall ≈ Rbig
– Cbig || Csmall ≈ Csmall
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Admin
• TA: Andrew Townley
– Email: atownley
– Office Hours:
seas
• Lecture Monday: building gates
– Reading
• Lab on Wednesday
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MOSFET
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Big Ideas
• MOSFET Transistor as switch
• Purpose-driven simplified modeling
– Aid reasoning
– Sanity check
– Simplify design
• New perspective on Rs and Cs
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