Transcript lect11a.ppt
A Scalable Approach to
Thread-Level Speculation
J. Gregory Steffan, Christopher B. Colohan,
Antonia Zhai, and Todd C. Mowry
Computer Science Department
Carnegie Mellon University
(Appeared in ISCA 2000.)
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Multithreaded Machines Are Everywhere
Threads
P
P
P
P
C
C
C
C
C
P
C
C
C
C
Shared Memory
SUN MAJC,
ALPHA 21464 Dual Pentium
IBM Power4
How can we use them?
P
P
C
C
C
C
Shared Memory
SGI Origin
Parallelism!
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Automatic Parallelization
Proving independence of threads is hard:
– complex control flow
– complex data structures
– pointers, pointers, pointers
– run-time inputs
How can we make the compiler’s job feasible?
Thread-Level Speculation (TLS)
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Example
Time
Processor
= hash[3]
…
hash[10] =
…
while (...){
= hash[19]
…
hash[21] =
…
x = hash[index1];
…
hash[index2] = y;
...
= hash[33]
…
hash[30] =
…
}
= hash[10]
…
hash[25] =
…
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Example of Thread-Level Speculation
Processor
Processor
Processor
Processor
Epoch 1
= hash[3]
…
hash[10] =
…
Time
Epoch 2
= hash[19]
…
hash[21] =
…
Epoch 3
= hash[33]
…
hash[30] =
…
Epoch 4
= hash[10]
…
hash[25] =
…
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Example of Thread-Level Speculation
Processor
Epoch 1
= hash[3]
…
hash[10] =
…
Time
Processor
Epoch 2
= hash[19]
…
hash[21] =
…
Processor
Epoch 3
= hash[33]
…
hash[30] =
…
Processor
Epoch 4
= hash[10]
…
hash[25] =
…
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Example of Thread-Level Speculation
Processor
Epoch 1
Time
= hash[3]
…
hash[10] =
…
commit?
Processor
Epoch 2
= hash[19]
…
hash[21] =
…
commit?
Processor
Epoch 3
= hash[33]
…
hash[30] =
…
commit?
Processor
Epoch 4
= hash[10]
…
hash[25] =
…
commit?
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Example of Thread-Level Speculation
Processor
Epoch 1
Time
= hash[3]
…
hash[10] =
…
commit?
Processor
Epoch 2
= hash[19]
…
hash[21] =
…
commit?
Processor
Epoch 3
= hash[33]
…
hash[30] =
…
commit?
Processor
Epoch 4
= hash[10]
…
hash[25] =
…
commit?
Epoch 4
Retry
= hash[10]
…
hash[25] =
…
commit?
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Goals of Our Approach
1) Handle arbitrary memory accesses
– i.e. not just array references
2) Preserve performance of non-speculative workloads
– keep hardware support minimal and simple
3) Apply to any scale of multithreaded architecture
– CMPs, SMT processors, more traditional MPs
effective, simple, and scalable TLS
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Overview of Our Approach
System requirements:
1) Detect data dependence violations
• extend invalidation-based cache coherence
2) Buffer speculative modifications
• use the caches as speculative buffers
coherence already works at a variety of scales
hence our scheme is also scalable
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Related Schemes
• Wisconsin (Multiscalar, Trace Processor)
• Stanford (Hydra)
• U.P. Catalunya (Speculative Multithreading)
• Intel/U. Portland (Dynamic Multithreading)
• Illinois at U.C. (I-ACOMA)
our approach seamlessly scales both up and down
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Outline
Details of our Approach
– life cycle of an epoch
– speculative coherence
– what happens at commit time
– forwarding data between epochs
• Performance
• Conclusions
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Life Cycle of an Epoch
Time
Spawned
Slow
Commit:
Init
Becomes
Speculative
Speculative
Work
Wait to be
Homefree?
Commit?
Fast
Commit:
Complete,
Pass Homefree
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Epoch Numbers
Thread Identifier (TID) Sequence Number
Represent a partial ordering
– signed-compare sequence numbers if TIDs match
• allows for wrap-around
– otherwise the epochs are unordered
• from independent programs
• from independent chains of speculation within one
program
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Speculative Thread Model
Round-robin schedule of epochs to processors
– not a requirement of our scheme, just for convenience
Each epoch spawns the next
– through a lightweight fork instruction (10 cycles)
Violations detected through polling
– each epoch runs to completion before detecting failed
speculation and restarting
Violation chaining
– if an epoch suffers a violation, we squash all logically-later
epochs
many possibilities to be evaluated in future work
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Preserving Correctness
Speculation must fail whenever speculative state is lost
– eg., replacement of a speculative line, ORB overflow
Any exceptions are suppressed until epoch is homefree
– eg., divide by zero, segfault
Polling violation detection must avoid infinite looping
– requires a poll inside each loop
No system calls while speculative (for now)
ensures original sequential semantics are preserved
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Life Cycle of an Epoch
Time
Spawned
Becomes
Speculative
Speculative
Coherence
Commit?
Mechanisms
to Squash
or Commit
Complete,
Pass Homefree
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MESI Coherence Example
Thread A:
Thread B:
Processor
Processor
Cache
State Tag Data
Invalid
-
Cache
State Tag Data
Invalid
-
Shared Memory (X=2)
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MESI Coherence Example
Thread A:
Thread B:
Load X
Processor
Processor
Cache
State Tag Data
Invalid
-
Cache
State Tag Data
Invalid
Read
Shared Memory (X=2)
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MESI Coherence Example
Thread A:
Thread B:
Processor
Load X
Processor
Cache
State Tag Data
Invalid
-
Cache
State
Excl.
Tag Data
X
2
Read Fill
Shared Memory (X=2)
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MESI Coherence Example
Thread A: Store X=3
Thread B:
Processor
Load X
Processor
Cache
State Tag Data
Invalid
-
Cache
State
Excl.
Tag Data
X
2
Read-Exclusive
Shared Memory (X=2)
read-exclusive invalidates all other copies
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MESI Coherence Example
Thread A: Store X=3
Thread B:
Load X
Processor
Processor
Cache
State Tag Data
Invalid
-
Cache
State Tag Data
Invalid
-
Read-Exclusive
Invalidation
Shared Memory (X=2)
read-exclusive invalidates all other copies
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MESI Coherence Example
Thread A: Store X=3
Thread B:
Processor
Cache
State
Dirty
Fill
Load X
Processor
Cache
State Tag Data
Invalid
-
Tag Data
X
3
Read-Exclusive
Shared Memory (X
Invalidation
)
the state ‘dirty’ implies exclusiveness
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Speculative Coherence Example
Epoch4:
Epoch5:
Epoch6:
Load X
Store X=3
Load X
Highlights of our scheme:
– detection of a data dependence violation
– speculatively modified and shared cache lines
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Speculative Coherence Example
Epoch5:
Epoch6:
Load X
Processor
Processor
Cache
State Tag Data
Invalid
-
Cache
State Tag Data
Invalid
Read
Shared Memory (X=2)
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Speculative Coherence Example
Epoch5:
Epoch6:
Processor
Load X
Processor
Cache
State Tag Data
Invalid
-
Cache
State
Excl.
Tag Data
X
2
Read
Spec.
Loaded
Fill
Shared Memory (X=2)
track which lines are speculatively loaded
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Speculative Coherence Example
Epoch5: Store X=3
Epoch6:
Processor
Load X
Processor
Cache
State Tag Data
Invalid
-
Cache
State
Excl.
Tag Data
X
2
Spec.
Loaded
Sp Read-Ex (epoch5)
Shared Memory (X=2)
speculative msgs piggyback epoch number
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Speculative Coherence Example
Epoch5: Store X=3
Epoch6:
Processor
Load X
Processor
Cache
State Tag Data
Invalid
-
Cache
State
Excl.
Tag Data
X
2
Sp Read-Ex (epoch5)
Spec.
Loaded
Sp Inv (epoch5)
Shared Memory (X=2)
epoch5 < epoch6, and speculatively loaded
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Speculative Coherence Example
Epoch5: Store X=3
Epoch6:
Load X
speculation
failed!
Processor
Processor
Cache
State Tag Data
Invalid
-
Cache
State Tag Data
Invalid
-
Sp Read-Ex (epoch5)
Sp Inv (epoch5)
Shared Memory (X=2)
speculation fails for epoch 6
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Speculative Coherence Example
Epoch5: Store X=3
Epoch6:
Processor
Cache
State
Spec.
Excl.
Modified
Fill
Load X
speculation
failed!
Processor
Cache
State Tag Data
Invalid
-
Tag Data
X
3
Sp Read-Ex (epoch5)
Sp Inv (epoch5)
Shared Memory (X=2)
track which lines are speculatively modified
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Speculative Coherence Example
Epoch4:
Epoch5:
Epoch6:
Load X
Store X=3
Load X
Highlights of our scheme:
– detection of a data dependence violation
– speculatively modified and shared cache lines
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Speculative Coherence Example
Epoch4:
Epoch5: Store X=3
Processor
Processor
Cache
State Tag Data
Invalid
-
Cache
State
Excl.
Tag Data
X
3
Spec.
Modified
Shared Memory (X=2)
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Speculative Coherence Example
Epoch4:
Epoch5: Store X=3
Load X
Processor
Processor
Cache
State Tag Data
Invalid
-
Cache
State
Excl.
Tag Data
X
3
Spec.
Modified
Read
Shared Memory (X=2)
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Speculative Coherence Example
Epoch4:
Epoch5: Store X=3
Load X
Processor
Processor
Cache
State Tag Data
Invalid
-
Cache
State
Tag Data
3
Shared X
Read
Spec.
Modified
notify shared
Shared Memory (X=2)
both speculatively modified and shared!
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Speculative Coherence Example
Epoch4:
Epoch5: Store X=3
Load X
Processor
Spec.
Loaded
Processor
Cache
State
Cache
State
Tag Data
2
Shared X
Fill
Tag Data
3
Shared X
Read
Spec.
Modified
notify shared
Shared Memory (X=2)
multiple versions of the same cache line
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Summary of New Speculative Line State
New cache line state:
– has it been speculatively loaded?
• detect dependence violations
– has it been speculatively modified?
• buffer speculative modifications
– is it in a speculative shared or exclusive state?
• important performance optimizations
What if a speculative cache line is replaced?
– speculation fails for that epoch
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Implementation of Speculative State
Processor
Cache
State
Tag Data
-
-
-
-
-
-
-
-
-
-
-
-
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Implementation of Speculative State
Processor
Speculatively
Loaded
Speculatively
Modified
Cache
SL SM
State
Tag Data
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
modest amount of extra space
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Life Cycle of an Epoch
Time
Spawned
Becomes
Speculative
Speculative
Coherence
Commit?
Mechanisms
to Squash
or Commit
Complete,
Pass Homefree
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When Speculation Fails
Processor
Flash
Reset
Cache
SL SM
1 0
State Tag Data
Sp Ex
*
*
1
0
Sp Sh
*
*
0
1
Sp Ex
*
*
1
1
Sp Sh
*
*
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When Speculation Fails
Processor
If Set then
Invalidate;
Flash Reset
Cache
SL SM
0 0
State
Excl
Tag Data
*
*
0
0
Shared
*
*
0
1
Sp Ex
*
*
0
1
Sp Sh
*
*
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When Speculation Fails
Processor
Cache
SL SM
0 0
State
Excl
Tag Data
*
*
0
0
Shared
*
*
0
0
Invalid
*
*
0
0
Invalid
*
*
quick bit operation
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Life Cycle of an Epoch
Time
Spawned
Becomes
Speculative
Speculative
Coherence
Commit?
Mechanisms
to Squash
or Commit
Complete,
Pass Homefree
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When Speculation Succeeds
Processor
Flash
Reset
Cache
SL SM
1 0
State Tag Data
Sp Ex
*
*
1
0
Sp Sh
*
*
0
1
Sp Ex
*
*
1
1
Sp Sh
*
*
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When Speculation Succeeds
Processor
Cache
SL SM
0 0
SM & Exclusive:
Become Dirty
State
Excl
Tag Data
*
*
0
0
Shared
*
*
0
1
Sp Ex
*
*
0
1
Sp Sh
*
*
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When Speculation Succeeds
Processor
SM & Shared:
Need Exclusive
Access
Cache
SL SM
0 0
State
Excl
Tag Data
*
*
0
0
Shared
*
*
0
1
Sp Ex
*
*
0
1
Sp Sh
*
*
want to avoid searching entire cache
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When Speculation Succeeds
Processor
Cache
SL SM
0 0
Tag Data ORB
*
*
*
Shared *
State
Excl
0
0
0
1
Sp Ex
*
*
0
1
Sp Sh
X
*
X
ownership required buffer (ORB)
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When Speculation Succeeds
Processor
Cache
SL SM
0 0
Tag Data ORB
*
*
*
Shared *
State
Excl
0
0
0
1
Sp Ex
*
*
0
1
Sp Sh
X
*
X
Upgrade-Request (X)
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When Speculation Succeeds
Processor
Cache
SL SM
0 0
If SM,
Become Dirty;
Flash Reset
Tag Data ORB
*
*
*
Shared *
State
Excl
0
0
0
1
Sp Ex
*
*
0
1
Sp Sh
X
*
Ack (X)
-
Upgrade-Request (X)
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When Speculation Succeeds
Processor
Cache
SL SM
0 0
Tag Data ORB
*
*
*
Shared *
State
Excl
0
0
0
0
Dirty
*
*
0
0
Dirty
X
*
-
flush the ORB, then quick bit operations
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Forwarding Data Between Epochs
Load X
Store X
Store X
Signal
With
Forwarding
Wait
Load X
• predictable dependences cause frequent violations
• compiler inserts wait-signal synchronization
synchronize to avoid violations
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Speculation in a Shared Cache
Why?
1) Shared-cache multithreaded architectures
• eg. simultaneous multithreading
2) Context switch to another chain of speculation
3) Start new epoch while current epoch waits to commit
How?
replicate the speculative context
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Support for Speculation in a Shared Cache
Processor
Cache
SL SM
- -
State
-
Tag Data ORB
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
replicate the speculative context
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Support for Speculation in a Shared Cache
Processor
Cache
SL SM
- -
SL SM
- -
State
-
Tag Data ORB
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ORB
replicate the speculative context
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Outline
• Details of our Approach
Performance
– simulation infrastructure
– single-chip multiprocessor performance
– scaling beyond chip boundaries
• Conclusions
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Simulation Infrastructure
Compiler system and tools based on SUIF
– help analyze dependences, insert synchronization
– produce MIPS binaries containing TLS primitives
Benchmarks (all run to completion)
– buk, compress95, ijpeg, equake
Simulator
– superscalar, similar to MIPS R10K
– models all bandwidth and contention
detailed simulation!
P
P
C
C
Crossbar
C
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Pipeline Parameters
Issue Width
4
Functional Units
2Int, 2FP, 1Mem, 1Bra
Reorder Buffer Size
32
Integer Multiply
12 cycles
Integer Divide
76 cycles
All Other Integer
1 cycle
FP Divide
15 cycles
FP Square Root
20 cycles
All Other FP
Branch Prediction
2 cycles
GShare (16KB, 8 history bits)
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Memory Parameters
Cache Line Size
32B
Instruction Cache
32KB, 4-way set-assoc
Data Cache
32KB, 2-way set-assoc, 2 banks
Unified Secondary Cache
2MB, 4-way set-assoc, 4 banks
Miss Handlers
8 for data, 2 for insts
Crossbar Interconnect
8B per cycle per bank
Minimum Miss Latency to
Secondary Cache
10 cycles
Minimum Miss Latency to Local
Memory
75 cycles
Main Memory Bandwidth
1 access per 20 cycles
Intra-Chip Communication Latency
10 cycles
Inter-Chip Communication Latency
200 cycles
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Benchmark Details: Regions and Epochs
Application
buk
compress95
ijpeg
equake
Unrolling
Factor
Avg. Insts.
per Epoch
Parallel
Coverage
8
81.0
22.8%
8
135.0
33.8%
1
196.7
24.6%
1
240.4
22.7%
32
1467.9
8.2%
1
80.8
2.2%
1
84.0
5.0%
1
100.3
6.7%
1
2925.5
39.3%
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Performance on a 4-Processor CMP
Overall
Region
Speedup
Parallel
Coverage
Program
Speedup
buk
2.26
56.6%
1.46
compress95
1.27
47.3%
1.12
equake
1.77
39.3%
1.21
ijpeg
1.94
22.1%
1.08
Application
program speedups are limited by coverage
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Performance on a 4-Processor CMP
2.5
2.26
Speedup
2
1.77
1.5
1.94
Region
1.27
1
0.5
0
buk
Parallel
56.6%
Coverage:
compress95
47.3%
equake
ijpeg
39.3%
22.1%
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Performance on a 4-Processor CMP
2.5
2.26
Speedup
2
1.94
1.77
Region
1.46
1.5
1.27
1.21
1.12
1.08
Program
1
0.5
0
buk
Parallel
56.6%
Coverage:
compress95
equake
ijpeg
47.3%
39.3%
22.1%
program speedups are limited by coverage
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Normalized Region Execution Time
Varying the Number of Processors
buk and equake are memory-bound
compress95 and ijpeg are computation-intensive
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Normalized Region Execution Time
Varying the Number of Processors
buk and equake scale well
passing the homefree token is not a bottleneck
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Performance of the ORB (on a 4-CMP)
Average
Flush
Latency
(cycles)
Average
Maximum
buk
13.95
2.38
9
compress95
0.04
0.01
8
equake
0.13
0.04
12
ijpeg
1.06
0.17
5
Application
ORB Size (entries)
a small ORB is sufficient
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Tracking Dependences Per Cache Line
Problem:
– analagous to false sharing: false violations
– write-after-write dependences also cause violations
• but not a true dependence!
Solution:
– track dependences at a word granularity
– have an SM and SL bit per word in each cache line
is per-word state worth the extra overhead?
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Tracking Dependences Per Cache Line
Does it do any good?
– not for our 4 benchmarks
– adding this support showed no improvement
Why not?
– buk and equake have random access patterns
– compress95 is heavily synchronized
– ijpeg is unrolled to avoid false sharing
existing techniques for avoiding false sharing
can address this problem
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Scaling Beyond Chip Boundaries
Node
Node
P
P
P
P
C
C
C
C
Crossbar
Crossbar
C
C
Shared Memory
200 Cycles
simulate architectures with 1, 2 and 4 nodes
Carnegie Mellon
A Scalable Approach to Thread-Level Speculation
68
Steffan
Normalized Region Execution Time
Scaling Beyond Chip Boundaries
multi-chip systems benefit from TLS
Carnegie Mellon
A Scalable Approach to Thread-Level Speculation
69
Steffan
Normalized Region Execution Time
Scaling Beyond Chip Boundaries
our scheme scales well
Carnegie Mellon
A Scalable Approach to Thread-Level Speculation
70
Steffan
Conclusions
The overheads of our scheme are low:
– mechanisms to squash or commit are not a bottleneck
– per-word speculative state is not always necessary
It offers compelling performance improvements:
– program speedups from 8% to 46% on a 4-processor CMP
– program speedups up to 75% on multi-chip architectures
It is scalable:
– coherence provides elegant data dependence tracking
seamless TLS on a wide range of architectures
Carnegie Mellon
A Scalable Approach to Thread-Level Speculation
71
Steffan