Transcript Slides (Testability Measures)

CONTROLLABILITY AND OBSERVABILITY
KALYANA R KANTIPUDI
VLSI TESTING ’05
TERM PAPER
4/26/05
Kantipudi: ELEC7250
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DEFINITIONS:
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Controllability: The difficulty of setting a particular logic signal
to 0 or 1
Observability: The difficulty of observing the state of a logic
signal
Applicable for both combinational and sequential testability measures.
Combinational Testability measures: Spatial domain
Sequential Testability measures: Temporal domain
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Kantipudi: ELEC7250
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Why we need them?
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We need testability information of a circuit
Why?
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DFT (Design-For-Testability)
We need module-level or Register-Transfer-level measures for this
Why?
There will be no independent gates in VLSI circuits
ATPG (Automatic Test Pattern Generation)
We need gate-level measures for this
Why?
We need to know the easily controllable and observable nodes in a ckt
Why?
4/26/05
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Kantipudi: ELEC7250
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Gate-level Testability Measures: SCOAP
L. H. Goldstein, "Controllability / Observability Analysis of Digital Circuits"
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combinational zero controllability (CC0)
combinational one controllability (CC1)
combinational observability (CO)
sequential zero controllability (SC0)
sequential one controllability (SC1)
sequential observability (SO)
Primary Inputs:
The combinational controllabilities(CC0 & CC1) are set to ‘1’
and all sequential controllabilities(SC0 & SC1) are set to ‘0’
Primary Outputs:
Both combinational and sequential observabilities are set to ‘0’
4/26/05
Kantipudi: ELEC7250
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NAND Gate:
But every ATMG has a restriction: It has to be linear. It cannot be NP-Complete
SCOAP: All inputs to all logic elements are independent
What about reconvergent
fan-outs?
A
CC1(I)
CC0(Z)
4/26/05
CC0(Z)
CC1(I)
Kantipudi: ELEC7250B
CC0(Z) = CC1(I) + 1
CC0(Z) = CC1(A) + CC1(B) + 1
= 2 CC1(I) + 1
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High level Testability Measures
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Module-level measures:
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Every module has its own characteristic Function
A probability spectrum from the truth-tables of prim. o/ps of modules
C & O values are calculated from the probability spectrum
Register-Transfer-level measures: (J. E. Stephenson and J. Grason ’76)
 As network of components interconnected by unidirectional links
 Two tasks:
 Control Task: Propagating controllability from the circuit primary inputs,
through other components, to the inputs of the component
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Observation Task: Propagating observability from the outputs of the component
through other components to the primary outputs of the circuit
 Controllability(CY) and Observability(OY) of each node is calculated using complex
formulae.
4/26/05
Kantipudi: ELEC7250
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TMEAS
Detection probability using
testability measures:
V. D. Agrawal and M. R. Mercer, “Testability Measures-What Do They Tell Us?”
Represented detection probability as an exponential function:
So, the fault coverage is given by:
Gives only a rough estimation of fault coverage.
Found that 70% of the hard-to-test faults are actually detectable.
Inference:
“Testability measures cannot be the only criteria for DFT.”
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Kantipudi: ELEC7250
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Future needs:
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Need for accurate testability measures
Need more ATMG tools like TMEAS and ITTAP
Conclusion:
The present accuracy of testability measures is not enough;
For them to be the only criteria in DFT
Dynamic testability measures will be of much more help for an ATPG.
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Kantipudi: ELEC7250
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