Transcript powerpoint

ELEC 2200-002
Digital Logic Circuits
Fall 2014
Logic Synthesis (Chapters 2-5)
Vishwani D. Agrawal
James J. Danaher Professor
Department of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
http://www.eng.auburn.edu/~vagrawal
[email protected]
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
1
Logic Synthesis
Definition: To design a logic circuit such
that it meets the specifications and can be
economically manufactured:
Performance – meets delay specification, or has
minimum delay.
Cost – uses minimum hardware, smallest chip
area, smallest number of gates or transistors.
Power – meets power specification, or consumes
minimum power.
Testablility – has no redundant (untestable) logic
and is easily testable.
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
2
Synthesis Procedure
Minimization – Obtain MSOP or MPOS. This is
also known as two-level minimization because
the result can be implemented as a two-level
AND-OR or NAND-NAND or NOR-NOR circuit.
Technology mapping – Considering design
requirements, transform the minimized form into
one of the technologically realizable forms:
Programmable logic array (PLA)
Standard cell library
Field programmable gate array (FPGA)
Others . . .
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
3
References on Synthesis
G. De Micheli, Synthesis and Optimization
of Digital Circuits, New York: McGraw-Hill,
1994.
S. Devadas, A. Ghosh and K. Keutzer,
Logic Synthesis, New York: McGraw-Hill,
1994.
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
4
Programmable Logic Array (PLA)
A direct implementation of multi-output
function as a two-level circuit in MOS
technology.
PLA styles:
NAND-NAND
NOR-NOR
Textbook, Chapter 5.
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
5
Example: Two-Output Function
Need four products: P1, P2, P3, P4
A
F1
0
4
12
A
F2
8
0
4
12
8
1
1
5
1
3
C
13
1
7
1
15
1
2
6
9
1
13
1
11
1
14
5
10
9
1
D
3
C
7
15
1
2
6
1
14
1
D
11
1
10
1
B
Fall 2014, Nov 3 . . .
B
ELEC2200-002 Lecture 6
6
Two-Level AND-OR Implementation
Also known as technology-independent circuit.
INPUTS
C
AND
OR
P1
F1
P2
A
P3
B
F2
P4
D
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
7
NAND-NAND Implementation
INPUTS
C
NAND
NAND
P1
F1
P2
A
P3
B
D
Fall 2014, Nov 3 . . .
F2
P4
ELEC2200-002 Lecture 6
8
A NAND Gate in nMOS Technology
VDD
VDD
Depletion
load
XY
VDD
Enhancement
load
XY
XY
X
X
X
Y
Y
Y
GND
GND
GND
R. C. Jaeger and T, N. Blalock, Microelectronic Circuit Design,
Boston: McGraw-Hill, 2008, Section 6.8.2.
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
9
NAND-NAND PLA
A
B
C
D
F1
F2
VDD
VDD
P1
VDD
P2
VDD
P3
VDD
P4
VDD
GND
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
10
NAND-NAND PLA SCHEMATIC
C
D
F1
F2
OUTPUTS
B
INPUTS
A
Transistors at
cross-points
P1
P2
P3
P4
AND-plane
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
OR-plane
11
Standard-Cell Design
Obtain two-level minimized form.
Map the design onto predesigned building blocks
called standard cells (technology mapping).
Standard-cell library contains predesigned logic
cells in the technology of manufacture. Examples
of technology:
90 nanometer CMOS
65 nanometer CMOS
45 nanometer CMOS
...
This is known as application-specific integrated
circuit (ASIC).
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
12
Technology Mapping
Find a common logic element, e.g., two-input
NAND gate or inverter (one-input NAND).
MSOP is converted into NAND-NAND circuit.
Split larger input gates into two-input NAND
gates and inverters.
Cover the circuit with standard cells, also
split into two-input NAND gates and inverters
(graph-matching).
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
13
A Typical Cell Library
Name
Area units (cost)
Inputs
Inverter
2
A
NAND2
3
A, B
NAND3
4
A, B, C
NAND4
5
A, B, C, D
AOI21
4
A, B, C
OAI21
4
A, B, C
AOI22
5
A, B, C, D
XOR
4
A, B
Output function, Z
ZA
Z  AB
Z  ABC
Z  ABCD
Z  AB  C
Z  ( A  B)C
Z  AB  CD
Z  AB  AB
S. Devadas, A. Ghosh and K. Keutzer, Logic Synthesis, New York: McGraw-Hill
1994, Section 7.7, pp. 185-198.
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
14
NAND3 Cell in Transistors
VDD
Z
A
B
C
GND
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
15
NAND3 Cell Graphs
Directed Acyclic
Graph (DAG)
(tree)
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
16
NAND4 Cell
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
17
AOI21 Cell
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
18
OAI21 Cell
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
19
AOI22 Cell in Transistors
VDD
A
Z
B
C
D
GND
Observe that in a CMOS circuit, any vector of input variables connects the output Z
either to GND or to VDD, giving it a value 0 or 1, respectively. Examiningthe pull-down
network, we notice that the output is connected to GND if AB = 1 or CD =1. That
gives the output function as, Z  AB CD . The cell, therefore, is AOI22.
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
20
AOI22 Cell
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
21
XOR Cell
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
22
Technology Mapping Procedure
Obtain MSOP.
Convert to two-level AND-OR circuit.
Transform to two-level NAND-NAND
circuit.
Transform to two-input NAND and inverter
tree network.
Perform an optimal pattern matching to
obtain a minimum cost tree covering.
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
23
Previous Example: 2-Level NAND
INPUTS
C
NAND
NAND
P1
F1
P2
A
P3
B
D
Fall 2014, Nov 3 . . .
F2
P4
ELEC2200-002 Lecture 6
24
A Simple Technology Mapping
NAND2 (3)
C
NAND2 (3)
(2)
F1
D
NAND3 (4)
B
(2)
P2
NAND3 (4)
F2
NAND2 (3)
A
Cost = 24
NAND2 (3)
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
25
Circuit is a Directed Acyclic Graph
(DAG)
C
P1
F1
A
P2
P3
B
D
Fall 2014, Nov 3 . . .
P4
ELEC2200-002 Lecture 6
F2
Each node is a
NAND gate.
26
Splitting into a Forest of Trees
C
D
B
F1
P2
C
P2
D
P2
A
F2
B
A
D
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
27
Splitting DAG into Trees (Forest)
C
D
F1
C
B
D
P2
P2
A
P2
B
A
F2
D
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
28
Two-Input NAND Trees
C
F1
D
P2
B
C
D
P2
P2
A
F2
B
A
D
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
29
Alternatively, in Graph Format
C
D
P2
F1
B
C
D
P2
P2
A
F2
B
A
D
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
30
An Improved Technology Mapping
C
D
(2)
OAI21 (4)
(2)
P2
Inverters
inserted
For pattern
matching B
F1
NAND3 (4)
C
D
P2
P2
NAND3 (4)
A
B
F2
(2)
A
D
Fall 2014, Nov 3 . . .
NAND2 (3)
Cost = 22
NAND2 (3)
ELEC2200-002 Lecture 6
31
Alternatively, in Graph Format
C
OAI21 (4)
D
(2)
Nodes inserted
For pattern matching
F1
P2
B
NAND3 (4)
C
P2
D
P2
NAND2 (3)
A
NAND3 (4)
F2
B
(2)
A
D
Fall 2014, Nov 3 . . .
NAND2 (3)
ELEC2200-002 Lecture 6
Cost = 22
32
Improved Technology Mapping
C
AOI21 (4)
(2)
D
NAND3 (4)
B
(2)
F1
P2
NAND3 (4)
F2
NAND2 (3)
A
Cost = 22
NAND2 (3)
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
33
Original Reference
K. Keutzer, “DAGON: Technology Binding
and Local Optimization by DAG matching,”
Proc. 24th Design Automation Conf.,
1987, pp. 341-347.
Fall 2014, Nov 3 . . .
ELEC2200-002 Lecture 6
34