Transcript ppt

It is Sufficient to Test 25% of
Faults
Vishwani D. Agrawal
Rutgers University, ECE Dept., Piscataway, NJ 08854, USA
[email protected]
http://cm.bell-labs.com/cm/cs/who/va
A. V. S. S. Prasad and Madhusudan V. Atre
Agere Systems, Bangalore 560066, India
[email protected] [email protected]
7th International Design & Test Workshops – VDAT’03
Bangalore, August 28-30, 2003
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Test Vector Generation
DUT
Fault Model
Generate fault list
Collapse fault list
Required
fault coverage
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Generate test vectors
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Definitions
• Given
– T1 is set of all tests for fault F1
– T2 is set of all tests for fault F2
• F1 dominates F2
T1
T2
• F1 and F2 are equivalent
T1=T2
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Structural Equ. and Dom.
• Structural Equivalence
a
b
a0 a1
c0 c1
b0
b
1 Dominance
• Structural
a0 a1
a
b
b0
b1
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c0 c1
c
c
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ISCAS’85 Circuits
Circuit
name
Total
faults
Collapsed faults (collapse ratio)
Equivalence*
Dominance**
C17
34
22 (0.65)
16 (0.47)
C432
864
524 (0.61)
449 (0.52)
C499
998
758 (0.76)
706 (0.71)
C1355
2710
1574 (0.58)
1210 (0.45)
C1908
3816
1879 (0.49)
1566 (0.41)
C2670
5276
2747 (0.52)
2318 (0.44)
C3540
7080
3428 (0.48)
2794 (0.39)
C5315
10630
5350 (0.50)
4500 (0.42)
C6288
12576
7744 (0.62)
5824 (0.46)
C7552
15012
7550 (0.50)
6134 (0.41)
* Fastest, Gentest, Hitec, TetraMax
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**Fastest
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Problem Statement
• Reduce the collapsed fault set below
40-60% level.
• Outline of method:
– Use hierarchical fault collapsing (ITC’02)
– Use functional dominance (ITC’03)
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Functional Dominance
T1 T2
f1
Always 0
f0
f2
f1 f 2 f0 + f1 f2 f0 = 0
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An Example
a0 a1
a
e0
b b0 b1
ee
1
d
c0 c1
c
f0 f1
d0 d1
Total faults = 12
Structural Equivalence collapsed faults = 8
Structural Dominance collapsed faults = 6
Three tests, {00,01,10}, cover all faults
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f
AND Gate
a
b
a0
b0
c0
a1
b1
c1
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a0 a1
c0 c1
c
b0 b1
Dominance
graph
Dominance
matrix
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a0 a1 b0 b1 c0 c1
a0
a1
b0
b1
c0
c1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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OR Gate
c
d
c0
d0
f0
c1
d1
f1
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c0 c1
f0 f1
f
d0 d1
Dominance
graph
Dominance
matrix
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c0 c1 d0 d1 f0 f1
c0
c1
d0
d1
f0
f1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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Fanout
a0 a1
a
e0
b b0 b1
ee
1
d
b0
d0
e0
b1
d1
e1
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c0 c1
c
d0 d1
Dominance
graph
Dominance
matrix
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f0 f1
e0 e1 b0 b1 d0 d1
e0 1
e1
b0
b1
d0
d1
1
1
1
1
1
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f
Dominance matrix of Circuit
a0 a1 b0 b1 c0 c1 d0 d1 f0 f1 e0 e1
a0
a1
b0
b1
c0
c1
d0
d1
f0
f1
e0
e1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Entries in black obtained from functional dominance expression.
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Transitive Closure of
Dominance matrix
a0 a1 b0 b1 c0 c1 d0 d1 f0 f1 e0 e1
a0
a1
b0
b1
c0
c1
d0
d1
f0
f1
e0
e1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Entries in orange are added in transitive closure.
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Dominance Fault Collapsing
a0 a1 b0 b1 c0 c1 d0 d1 f0 f1 e0 e1
a0
a1
b0
b1
c0
c1
d0
d1
f0
f1
e0
e1
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1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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Dominance Collapsed Set
a0 a1
a
e0
b b0 b1
ee
1
d
c0 c1
c
f0 f1
d0 d1
Total faults = 12
Structural Equivalence collapsed faults = 8
Structural Dominance collapsed faults = 6
Functional dominance collapsed faults = 4
Two tests, {01,10}, cover all faults
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f
8-bit Ripple Carry Adder (RCA)
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XOR Cell
Functional Dom. examples: d0
c0 c1
c
a
d0
d1
b
e
d
f
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h
j0, k1
g0
j
g
m
i
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Collapsed Dominance Matrix
of XOR Cell
a0
Inputs
Collapsed
faults
Output
a0
a1
b0
b1
c0
c1
d0
d1
m0
m1
1
1
1
a1
1
1
1
b0
1
1
1
b1
c0
1
1
1
1
c1
1
d0
d1 m0 m1
1
1
1
1
1
1
1
1
24x24 matrix is reduced to a 10x10 matrix.
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Fault Collapsing Using
Functional Dominance
Number of collapsed faults
Circuit
name
All faults
Structural
Functional
equivalence
dominance
xor cell
24
16 (0.67)
4 (0.17)
Full-adder
60
38 (0.63)
14 (0.23)
8-bit adder
466
290 (0.62)
112 (0.24)
C499exp*
2710
1574 (0.58)
586 (0.22)
* C499exp implements C1355 with XOR cells.
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Conclusion
• Functional dominances can be found for
small cells and then applied via
hierarchical collapsing to large circuits.
• With functional dominances, the number
of faults for ATPG reduces to about 25%;
usually gives smaller test set.
• Caution: fault coverage may not be correct
when the collapsed fault set contains
redundant faults; coverage may be
evaluated for equivalence collapsed set.
• References: Prasad et al., ITC’02, pp. 391397; Agrawal et al., ITC’03.
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