Transcript ppt
A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets A. V. S. S. Prasad Agere Systems, Bangalore 560066, India [email protected] Vishwani D. Agrawal Agere Systems, Murray Hill, NJ 07974, USA [email protected] Madhusudan V. Atre Agere Systems, Bangalore 560066, India [email protected] 9-Oct-2002 Prasad et al., ITC'02 1 Talk Outline • Introduction – Background – Problem statement • A new graph model – Dominance graph – Transitive closure – Extraction of equivalence and dominance sets • • • • Functional equivalence Hierarchical fault collapsing Benchmark results Conclusion 9-Oct-2002 Prasad et al., ITC'02 2 Test Vector Generation Flow DUT Fault Model Generate fault list Collapse fault list Required fault coverage 9-Oct-2002 Generate test vectors Prasad et al., ITC'02 3 Background • Single stuck-at fault model is the most popularly used model. • Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2 (f1=f2) • If all tests of fault f1 also detect fault f2, then f2 is said to dominate f1 (f1f2). a0 a1 b0 b1 9-Oct-2002 c0 c1 a0 = b0 = c0 : Equivalence a1 c1 b1 c1 : Dominance : Dominance Prasad et al., ITC'02 4 Background • Both equivalence and dominance relations are transitive in nature. [ (f1 f2) and (f2 f3) => (f1 f3) ] • If f1 dominates f2 and f2 dominates f1 then f1 and f2 are equivalent. [ (f1 f2) and (f2 f1) => (f1 = f2) ] • Number of faults in a 2-input AND gate reduces from 6 to 4 (by equivalence) and to 3 (by dominance) collapsing. Example: ISCAS’85 Circuit - C6288, #faults = 10630, #faults (dominance collapsed) = 5824 9-Oct-2002 Prasad et al., ITC'02 5 Problem Statement • To devise a new method for fault collapsing with following attributes: – A single procedure for equivalence and dominance – Global analysis (independence from direction, and other choices, in collapsing) – Functional equivalence – Hierarchical fault collapsing (collapsing in large circuits using pre-collapsed sub networks) 9-Oct-2002 Prasad et al., ITC'02 6 A New Dominance Graph Model • A fault in the circuit is represented by a node in the graph. • A directed edge from f2 to f1 indicates that f1 dominates f2 (f2 f1). • Edges can represent either structural or functional relations. 9-Oct-2002 Prasad et al., ITC'02 7 Computational Model • Graph is represented as a connectivity matrix • Each fault is assumed to be equivalent to itself • Treats functional and structural relations identically • (f1 f2) and (f2 f1) => f2 = f1. Appear as symmetrical components in the matrix (e.g., a0,b0,c0) • #faults = 6 (dimension of 2-input AND gate dominance matrix) 9-Oct-2002 Prasad et al., ITC'02 8 Transitive Closure • Transitive closure (TC) of the dominance matrix gives all dominance relations between faults. • TC is computed by the O(n3) FloydWarshall algorithm, where n is the dimension of the dominance matrix. 9-Oct-2002 Prasad et al., ITC'02 9 Transitive Closure • (F1 F2) and (F2 F3) => (F1 F3) F1 F2 F3 Graph F1 F2 F3 9-Oct-2002 F1 F2 1 1 1 F1 F2 F3 Transitive Closure F3 F1 1 F2 1 F3 Prasad et al., ITC'02 F1 F2 F3 1 1 1 1 1 1 10 Example A D E B C Dominance Graph Transitive closure edges D0 A0 9-Oct-2002 E1 E0 C0 B0 D1 A1 Prasad et al., ITC'02 C1 B1 11 XOR Circuit c1 h1 g1 m0 g0 i1 f1 Functional Equivalences : (c1,f1), (g1,h1,i1), (g0,m0) 9-Oct-2002 Prasad et al., ITC'02 12 (24x24) Dominance matrix (XOR) Functional equivalences shown as boxed entries 9-Oct-2002 Prasad et al., ITC'02 13 Transitive Closure (XOR) j0 k0 m1 f1 f0…c1 a0 9-Oct-2002 Prasad et al., ITC'02 14 Results for XOR Circuit #faults #Eq. Faults #Dom. faults 24 16 13 With functional equivalence #faults #Eq. Faults #Dom. faults 24 9-Oct-2002 12 Prasad et al., ITC'02 10 15 Summary of Approach • Identify all the primary relations (structural and functional) • Construct the dominance graph and represent the same using connectivity matrix • Compute Transitive Closure (TC) • Extract equivalence and dominance sets from TC 9-Oct-2002 Prasad et al., ITC'02 16 Features • Global in nature (single procedure to treat equivalence and dominance collapsing) • Functional relations can easily be incorporated • Independent of the order of selecting the faults 9-Oct-2002 Prasad et al., ITC'02 17 Design Hierarchy • Large designs are modular and hierarchical. Top module B1 B1 C0 C0 C0 C0 C1 C1 B0 • Advantageous to store the fault information of repeated blocks in a library. • When configured as a library cell the fault list includes cell PI & PO faults for transitivity. 9-Oct-2002 Prasad et al., ITC'02 18 XOR Library Cell • Useful for hierarchical fault collapsing • Dimension of the matrix = 14 9-Oct-2002 Prasad et al., ITC'02 19 8-bit Ripple Carry Adder (RCA) 9-Oct-2002 Prasad et al., ITC'02 20 Faults in 8-bit RCA Number of collapsed faults Circuit name All faults Flat Hierarchical structural only with functional Equ. Dom. Equ. Dom. Xor cell 24 16 13 12 10 Full-adder 60 38 30 30 24 8-bit adder 466 290 226 226 178 9-Oct-2002 Prasad et al., ITC'02 21 ISCAS’85 Circuits Circuit name Total faults Equivalence fault set size Dominance fault set size Graph method Other programs* Graph method Fastest C17 34 22 22 16 16 C432 864 524 524 449 449 1044 560 632 449 503 998 758 758 706 706 C499exp 2710 1158 1574 898 1210 C1355 2710 1574 1574 1210 1210 C1908 3816 1879 1879 1566 1566 C2670 5276 2747 2747 2317 2318 C3540 7080 3428 3428 2786 2794 C5315 10630 5350 5350 4492 4500 C6288 12576 7744 7744 5824 5824 C7552 15012 7550 7550 * Fastest, Gentest, Hitec, TetraMax 6132 6134 C432exp C499 9-Oct-2002 Prasad et al., ITC'02 22 Conclusion • A new algorithm for global fault collapsing • With functional equivalence number of faults for ATPG reduces considerably • Library based hierarchical fault collapsing is a new concept • Further studies are being carried out on: – Functional dominance – Independent fault sets 9-Oct-2002 Prasad et al., ITC'02 23