Transcript Poster by Jiang and Agrawal

Designing Variation-Tolerance in Mixed-Signal Components
of a System-on-Chip
Wei Jiang and Vishwani D. Agrawal
Electrical and Computer Engineering, Auburn University, Auburn, AL, 36849
• Process variation in nanoscale technology
– Catastrophic faults
– Parametric faults, more than before, cause
Analog output
• Built-in self-test and self-calibration
Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
[email protected], [email protected]
– Analog-to-digital converter (ADC)
– Digital-to-analog converter (DAC)
DAC
under-test
DSP
Devices
Under
Test
Analog input
– Test and diagnosis
– Device calibration
Based on a paper presented at the
IEEE International Symposium on Circuits and Systems
Taipei, Taiwan, May 24-27, 2009
Analog
signals
Analog
System
Input
and
Output
• Degraded performance
• Yield reduction
Wei Jiang and Vishwani D. Agrawal
ANALOG
SYSTEM
ANALOG
SYSTEM
Analog
signals
ADC
Digital input
DIGITAL
SYSTEM
Digital
System
Input and
Output
• Non-linearity errors in kth output:
Analog
System
Input
and
Output
– Differential non-linearity (DNL)
– Integral non-linearity (INL)
under-test
DNLk 
MIXED SIGNAL
• Characteristics measurement
• On-chip error correction
Analog output
 k  k 1
LSB
1
i 1
LSB
Portions of a typical wireless transceiver SoC.
June 1-2, 2009
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Proposed BIST Scheme
DAC
under-test
Corrected
analog
output
Analog
correction signal
d-DAC
Digital output
y
Polynomial eval
x
Analog
loopback
Measuring
ADC
MIXED SIGNAL
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TPG
DSP
Polynomial coefficients for DAC
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• The fitting procedure is off-line, done
– At system startup, after digital BIST for DSP is completed.
– Periodically when system is idle, to continuously update fitting polynomial
*S. K. Sunter and N. Nagi, “A simplified Polynomial-Fitting Algorithm for DAC and
ADC BIST,” Proc. of International Test Conference, 1997, paper 16.2.
†W. Jiang and V. D. Agrawal, “Built-in Adaptive Test and Calibration of DAC,” Proc.
IEEE 18th North Atlantic Test Workshop, May 2009, pp. 3-8.
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• Future Work
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• Authors will appreciate your questions or
comments.
• Please write to:
– Wei Jiang, [email protected]
– Vishwani D. Agrawal [email protected]
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ANALOG
SYSTEM
MUX
ADC
ORA
DIGITAL
SYSTEM
Digital
System
Input and
Output
Digital input
under-test
BIST
Results
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• Testing of on-chip ADC:
– Use calibrated DAC to test and characterize on-chip
ADC under test.
– For details, see Proc. ISACS’09.
– Also see, W. Jiang and V. D. Agrawal, “Built-in SelfCalibration of On-Chip DAC and ADC,” Proc.
International Test Conference, 2008, paper 32.2.
• Later work,
– W. Jiang and V. D. Agrawal, “Built-in Adaptive Test
and Calibration of DAC,” Proc. 18th IEEE North
Atlantic Test Workshop, May 13-15, 2009, pp. 3-8.
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This research is supported in parts
by the National Science Foundation
Grant CNS-0708962 and the
Wireless Engineering Research and
Education Center at Auburn
University.
– Reliable self-test for test and calibration circuitry
(sigma-delta modulator, dithering DAC, etc.)
– Generalize the polynomial interpolation of INL to
higher degree polynomials.
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Response
control
MUX
DSP
TEST
CONTROL
More Details and Subsequent Work
Thank you
• Proposed technique
Loopback
controls
See, F. F. Dai and C. E. Stroud, “Analog and Mixed-Signal Test Architectures,”
Chapter 15, p. 722 in System-on-Chip Test Architectures: Nanometer Design
for Testability, Morgan Kaufmann, 2008.
• Stored polynomial coefficients are stored in digital
registers by off-line measurement.
• Correction for analog INL error for each digital
input are generated by a low-resolution dithering
DAC
• This limits the INL error in the calibrated DAC
output to within 0.5 LSB.
• To avoid nonlinearity errors within dithering-DAC,
dynamic element matching (DEM) techniques may
be investigated.
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Devices
Under
Test
TPG
Test pattern
control
k
DAC Output Correction (On-Line)
Conclusion and Future Work
– Uses simple devices for a post-fabrication technique to
improve system reliability against process-variation.
– Off-line built-in fault-detection and parameter
characterization.
– On-line at-speed self-correction for nonlinearity errors.
Indices of 14-bit DAC-under-test
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3
– Third-order polynomial as, y=b0+b1x+b2x2+b3x3
– A simple algorithm* partitions DAC outputs into four equal-sized sections
and calculates sums for each section.
– Obtaining four polynomial coefficients from the sums
– Characteristics of DAC (offset, gain, 2nd and 3rd harmonic distortions) can
generally be identified with these coefficients.
– Higher degrees for the polynomial can be used if an adaptive fitting
algorithm is used.†
• Polynomial
fitting for DAC
output
• 6-bit low cost
dithering-DAC
• INL error
reduced to
±0.5LSB
INL of 14-bit DAC (LSB)
INL of 14-bit DAC (LSB)
• 16K ramp codes
• Maximum INL error up to ±1.5 LSB
June 1-2, 2009
• Fitting INL error of DAC output
Polynomial Fit and Calibrated DAC
Indices of 14-bit DAC-under-test
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Polynomial Fitting Algorithm (Off-Line)
• The on –chip DSP provides all codes to the DAC under
test.
• A 1-bit ΣΔ modulator does A-to-D conversion.
• High linearity due to oversampling and noise shaping
technique.
• Assumption: ΣΔ modulator is fault-free because of its
simple structure and good tolerance for quantization
errors.
• ΣΔ is modulator is deactivated during normal system
operation; no performance impact on SoC.
• Use of higher-order ΣΔ modulator may have
advantages, to be investigated.
ORA
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June 1-2, 2009
DAC Output Measurement (Off-Line)
A 14-Bit DAC with Nonlinearity
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under-test
MUX
MIXED SIGNAL
where LSB = magnitude of least significant bit
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DAC
under-test
Analog input
 k  0
Digital output
Analog signals
Analog
Loopbacks
MUX
k
INLk   DNLk 
ANALOG
SYSTEM
Digital loopback
• Mixed-signal Devices on SoC
Analog loopback
Designing Variation-Tolerance in
Mixed-Signal Components of a
System-on-Chip
Mixed-Signal Devices Under Test
A Conventional Mixed-Signal BIST
Architecture
Analog system loopback
Motivation
Mixed-Signal Components and Errors
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