Transcript VLSI D&T Seminar (Fall'07), Using Hierarchy in Design Automation: The Fault Collapsing Problem (VDAT'07)

Using Hierarchy in Design Automation:
The Fault Collapsing Problem
Raja K. K. R. Sandireddy
Vishwani D. Agrawal
Intel Corporation
Hillsboro, OR 97124, USA
Auburn University
Auburn, AL 36849, USA
[email protected]
[email protected]
11th VLSI Design and Test Symposium
Kolkata, August 8-11, 2007
Outline
• Introduction
– Main idea
– Background on fault collapsing
• Hierarchical fault collapsing
– Method
– Advantages:
• Smaller collapse ratio
• Reduced CPU time
• Results
• Conclusion
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The General Idea of Hierarchy
Circuit
(top level
In hierarchy)
Subnetwork
analyzed once,
placed in library.
Analysis at nth level:
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interconnects
Lowest-level
block (gates and
interconnects),
analyzed in
detail, saved in
library.
1. Copy preprocessed internal detail of n-1 level
from library.
2. Process nth level interconnects.
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Background on Fault Collapsing
Test Vector Generation Flow
DUT
Fault model
Generate fault list
Collapse fault list
Required fault
coverage
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Generate test vectors
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Structural Fault Collapsing
a0 a1
c0 c1
Total faults = 6
b0 b1
• Equivalence Collapsing:
It is the process of selecting one
fault from each equivalence fault set.
– Equivalence collapsed set = {a0, b0, c0, c1}
– Collapse ratio = 4/6 = 0.67
• Dominance Collapsing:
From the equivalence collapsed
set, all dominating faults are left out retaining their respective
dominated faults.
– Dominance collapsed set = {a0, b0, c1}
– Collapse ratio = 3/6 = 0.5
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An Example of Structural Collapsing
a0 a1
a
e0
b0 b1
b
e
e1
d
c0 c1
c
f0 f 1
f
d0 d1
Total faults = 12
Structural Equivalence collapsed faults = 8
Structural Dominance collapsed faults = 6
Three tests, {00,01,10}, cover all faults
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Functional Collapsing
• Two faults are functionally equivalent if the
corresponding faulty functions are identical.
• Functional dominance can be similarly defined.
• Determination of functional equivalence or dominance
is as complex as test generation or equivalence
checking.
• A graph-theoretic method for fault collapsing:
– A. V. S. S. Prasad, V. D. Agrawal and M. V. Atre, “A New
Algorithm for Global Fault Collapsing into Equivalence and
Dominance Sets,” Proc. Int. Test Conf., 2002, pp. 391-397.
– V. D. Agrawal, A. V. S. S. Prasad and M. V. Atre, “Fault
Collapsing via Functional Dominance,” Proc. Int. Test Conf.,
2003, pp. 274-280.
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Dominance Collapsed Set
a0 a1
a
e0
b b0 b1
e
e1
d
c0 c1
c
f0 f1
d0 d1
Total faults = 12
Structural Equivalence collapsed faults = 8
Structural Dominance collapsed faults = 6
Functional dominance collapsed faults = 4
Two tests, {01,10}, cover all faults
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f
Functional Collapsing: XOR Cell
Functional dominance examples: d0 → j0, k1 → g0
c0 c1
c
a
d0
d1
b
e
d
f
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h
j
g
All faults = 24
Str. Equ. Faults = 16
Str. Dom. Faults = 13
Func. Dom. Faults = 4
m
i
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Hierarchical Fault Collapsing
• Create a library
– For smaller (gate-level) circuits, exhaustive (functional)
collapsing may be done.
– For larger circuits, use structural collapsing.
• For hierarchical circuits, at any level of hierarchy, say
nth level:
– Read-in preprocessed (library) collapse data of (n-1) level
sub-circuits.
– Structurally collapse the interconnects and gate faults of nth
level.
- R. K. K. R. Sandireddy and V. D. Agrawal, “Diagnostic and Detection Fault
Collapsing for Multiple Output Circuits,” Proc. Design, Automation and Test in
Europe Conf., March 2005, pp. 1014–1019.
- R. Hahn, R. Krieger, and B. Becker, “A Hierarchical Approach to Fault
Collapsing,” Proc. European Design & Test Conf., 1994, pp. 171–176.
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A Fault Collapsing Library
Cell characteristics
Cell
name
Collapsed fault set size
No. of No. of No. of Total
inputs outputs gates faults
Structural
Functional
Equ Dom Equ Dom
Func.
coll.
CPU
(s)*
Logic
gates
n
1
1
2n+2
n+2
n+1
n+2
n+1
-
XOR
2
1
4
24
16
13
10
4
7.9
HA
2
2
5
30
20
16
15
6
9.1
FA
3
2
11
60
38
30
26
12
15.7
* Sun Ultrasparc 5_10 (360MHz, 128MB)
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Collapse ratio
Collapse Ratios for Ripple-Carry
Adders
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Total faults
Structural Equiv.
Hierarchical Equiv.
Structural Dom.
Hierarchical Dom.
4-bit
Adder
32-bit
Adder
256-bit 2048-bit 8192-bit
Adder Adder Adder
234
1,858
14,850 118,786 475,138
In hierarchical collapsing, faults in lowest level cells (XOR, full-adder,
half-adder) are functionally collapsed.
Programs used: 1. Hitec (obtained from Univ. of Illinois at Urbana-Champaign)
2. Fastest (obtained from Univ. of Wisconsin at Madison)
3. Our program (Auburn Univ.)
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CPU Time (sec) Improvement by
Hierarchy for Ripple-Carry Adder
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Rent’s rule
• Rent’s Rule: Number of inputs and outputs
terminals (T) for a typical block containing G
logic gates is given by:
G is
proportional
T = K × Gα
to area
α ~ 0.5 to 0.65
• CPU time for collapsing a large hierarchical
circuit is dominated by the time taken to build
the structure of the circuit which is proportional
to the T 2 (ref: our previous work).
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Hierarchical 8-Bit Ripple Carry Adder
Here α ~ 1.0, hence the total collapse time is quadratic in circuit size as
observed in our experiment.
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Hierarchical Array Multiplier
n × n multiplier
n/2×n/2
n/2×n/2
n/2×n/2
n/2×n/2
Outputs
Inputs
Additional Circuitry
prop. to √G
prop. to √G
Here α ~ 0.5, hence we expect the total collapse time to grow linearly
with circuit size.
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Collapse ratio
Collapse Ratios for Array Multipliers
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Structural Equiv.
Hierarchical Equiv.
Structural Dom.
Hierarchical Dom.
2*2
4*4
8*8 16*16 32*32 64*64 128
mult. mult. mult. mult. mult. mult. mult.
Total faults
84
726
3762
16,842 71,034 291,546 1,181,082
In hierarchical collapsing, faults in lowest level cells (XOR, full-adder,
half-adder) are functionally collapsed.
Programs used: 1. Hitec (obtained from Univ. of Illinois at Urbana-Champaign)
2. Fastest (obtained from Univ. of Wisconsin at Madison)
3. Our program (Auburn Univ.)
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CPU Time Improvement by Hierarchy for
Array Multipliers
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Conclusion
• Benefits of hierarchical fault collapsing:
– Better (lower) collapse ratios due to functional collapsing of
library cells.
– Order of magnitude reduction in collapse time.
• Possible benefits of smaller fault sets:
– Fewer test vectors
– Efficient fault simulation
– Easier fault diagnosis
• Further investigations:
128-bit multiplier
Dom. Collapsed Set Size
(Collapse Ratio)
Flat
Hierarchical
CPU s
Flat
53,4284 (0.45) 26,5824 (0.23) 27645
Hier
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– Structural problems (testability measures, static timing
analysis, physical design, etc.) may be solved using hierarchy.
– Functional problems (ATPG, simulation, etc.) may require
new hierarchical algorithms.
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