Transcript Lecture 2: Yield and Quality

VLSI Testing
Lecture 2: Yield & Quality
Dr. Vishwani D. Agrawal
James J. Danaher Professor of Electrical and
Computer Engineering
Auburn University, Alabama 36849, USA
[email protected]
http://www.eng.auburn.edu/~vagrawal
IIT Delhi, Aug 17, 2013, 11:00AM-12:00PM
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Contents
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Yield and manufacturing cost
Clustered defect yield formula
Defect level
Test data analysis
Example: SEMATECH chip
Summary
Problems to solve
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VLSI Chip Yield
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A manufacturing defect is a finite chip area with
electrically malfunctioning circuitry caused by
defects created by the fabrication process.
A chip with no manufacturing defect is called a good
chip.
Fraction (or percentage) of good chips produced in a
manufacturing process is called the yield. Yield is
denoted by symbol Y.
Cost of a chip:
Cost of fabricating and testing a wafer
———————————————————————
Yield x Number of chip sites on the wafer
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Clustered VLSI Defects
Good chips
Faulty chips
Defects
Wafer
Unclustered defects
Wafer yield = 12/22 = 0.55
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Clustered defects (VLSI)
Wafer yield = 17/22 = 0.77
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Yield Parameters
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Defect density (d ) = Average number of defects per
unit of chip area
Chip area (A)
Clustering parameter (α)
Negative binomial distribution of defects,
p (x ) = Prob (number of defects on a chip = x )
(Ad /a) x
= ─────── . ──────────
x ! G (a)
(1+Ad /a) a+x
where Γ is the gamma function
a = 0, p (x ) is a delta function (maximum clustering)
a = ∞ , p (x ) is Poisson distribution (no clustering)
G (a+x )
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Yield Equation
Y = Prob ( zero defect on a chip ) = p (0)
Y = ( 1 + Ad / a ) - a
Example: Ad = 1.0, α = 0.5, Y = 0.58
Unclustered defects: α = ∞, Y = e
– Ad
Example: Ad = 1.0, α = ∞, Y = 0.37
too pessimistic !
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Defect Level or Reject Ratio
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Defect level (DL) is the ratio of faulty chips among
the chips that pass tests.
DL is measured as parts per million (ppm).
DL is a measure of the effectiveness of tests.
DL is a quantitative measure of the manufactured
product quality. For commercial VLSI chips a DL
greater than 500 ppm is considered unacceptable.
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Determination of DL
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From field return data: Chips failing in the field
are returned to the manufacturer. The number of
returned chips normalized to one million chips
shipped is the DL.
From test data: Fault coverage of tests and chip
fallout rate are analyzed. A modified yield model
is fitted to the fallout data to estimate the DL.
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Modified Yield Equation
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Three parameters:
 Fault density, f = average number of stuck-at
faults per unit chip area
 Fault clustering parameter, β
 Stuck-at fault coverage, T
The modified yield equation:
Y (T ) = (1 + TAf / b) – b
Assuming that tests with 100% fault coverage
(T = 1.0) remove all faulty chips,
Y = Y (1) = (1 + Af / b) – b
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Defect Level
Y (T ) – Y (1)
DL (T ) = ———————
Y (T )
b
( b + TAf )
= 1 – ——————
b
( b + Af )
Where T is the fault coverage of tests, Af is the
average number of faults on the chip of area A, β
is the fault clustering parameter. Af and β are
determined by test data analysis.
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Example: SEMATECH Chip
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Bus interface controller ASIC fabricated and
tested at IBM, Burlington, Vermont
116,000 equivalent (2-input NAND) gates
304-pin package, 249 I/O
Clock: 40MHz, some parts 50MHz
0.8m CMOS, 3.3V, 9.4mm x 8.8mm area
Full scan, 99.79% fault coverage
Advantest 3381 ATE, 18,466 chips tested at
2.5MHz test clock
Data obtained courtesy of Phil Nigh (IBM)
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Stuck-at fault coverage, T
Test Coverage from
Fault Simulator
Vector number
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Measured chip fallout, 1 – Y (T )
Measured Chip Fallout
Vector number
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Chip fallout and computed 1 – Y (T )
Model Fitting
Chip fallout vs. fault coverage
Y (1) = 0.7623
Measured chip fallout
Y (T ) for Af = 2.1 and b = 0.083
Stuck-at fault coverage, T
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Computed DL
Defect level in ppm
237,700 ppm (Y = 76.23%)
Stuck-at fault coverage (%)
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Summary
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VLSI yield depends on two process parameters, defect
density (d ) and clustering parameter (α).
Yield drops as chip area increases; low yield means
high cost.
Fault coverage measures the test quality.
Defect level (DL) or reject ratio is a measure of chip
quality.
DL can be determined by an analysis of test data.
For high quality: DL << 500 ppm, fault coverage ~ 99%
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Two Problems to Solve
1.
Using the expression for defect level on Slide 10,
derive test coverage (T ) as a function of fault
clustering parameter (β), defect level (DL), and
average number of faults (Af ) on a chip.
2.
Find the defect level for:
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Fault density, f = 1.45 faults/sq. cm
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Fault clustering parameter, β = 0.11
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Chip area = 1 cm2
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Fault Coverage, T = 95%
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Solution to Problem 1
Defect level, DL, is given on Slide 10, as follows:
DL = 1 – [(β + TAf )/(β + Af )]β
where T is the fault coverage, Af is the average number of
faults on a chip of area A, and β is a fault clustering
parameter. Further manipulation of this equation leads to the
following result:
(1 – DL)1/β = (β + TAf )/(β + Af )
or
T = [{(β + Af )(1 – DL)1/β – β}/(Af )] × 100 percent
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Solution to Problem 2
Defect level, DL, as given on Slide 10, is:
DL(T ) = 1 – [(β + TAf )/(β + Af )]β
Substituting,
 Fault density, f = 1.45 faults/sq. cm
 Fault clustering parameter, β = 0.11
 Chip area = 1 cm2
 Fault Coverage, T = 95%
We get,
DL(T ) = 0.00522 or 5,220 parts per million
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