Transcript Lecture 12: Sequential Circuit ATPG -- Time-Frame Expansion

Lecture 13
Sequential Circuit ATPG
Time-Frame Expansion
(Lecture 12alt in the Alternative Sequence)
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Problem of sequential circuit ATPG
Time-frame expansion
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Nine-valued logic
ATPG implementation and drivability
Complexity of ATPG
Cycle-free and cyclic circuits
Asynchronous circuits
Summary and Exercise
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VLSI Test: Lecture 13/12alt
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Sequential Circuits
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A sequential circuit has memory in addition to
combinational logic.
Test for a fault in a sequential circuit is a
sequence of vectors, which
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Initializes the circuit to a known state
Activates the fault, and
Propagates the fault effect to a primary output
Methods of sequential circuit ATPG
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Time-frame expansion methods
Simulation-based methods
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Example: A Serial Adder
An Bn
1
1
s-a-0
D
1
1
D
X
Cn
Cn+1
X
1
Combinational logic
Sn X
FF
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Time-Frame Expansion
An-1 Bn-1
1
1
An Bn
Time-frame -1
1
s-a-0
D
1
X
1
Cn-1
Time-frame 0
s-a-0
D
D
1
1
D
X
Cn
X
1
D
1
Cn+1
1
Combinational logic
Combinational logic
Sn-1
1
Sn
X
D
FF
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Concept of Time-Frames
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If the test sequence for a single stuck-at fault
contains n vectors,
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Fault
Unknown
or given
Init. state
Comb.
block
Replicate combinational logic block n times
Place fault in each block
Generate a test for the multiple stuck-at fault using
combinational ATPG with 9-valued logic
Vector – n +1
TimeState
Frame variables
- n+1
PO – n +1
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Vector – 1
Vector 0
Timeframe
-1
Timeframe
0
PO – 1
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Next
state
PO 0
5
Example for Logic Systems
FF1
A
B
FF2
s-a-1
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Five-Valued Logic (Roth)
0,1, D, D, X
A 0
A 0
s-a-1
s-a-1
D
FF1
FF2
D
X
X
X
X
D
D
Time-frame -1
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B
X
Time-frame 0
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B
FF1
FF2
X
7
Nine-Valued Logic (Muth)
0,1, 1/0, 0/1, 1/X, 0/X, X/0, X/1, X
A 0
A X
s-a-1
s-a-1
X/1
0/1
FF1
FF2
X
0/X
0/X
X
0/1
X/1
Time-frame -1
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B
X
Time-frame 0
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B
FF1
FF2
0/1
8
Implementation of ATPG
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Select a PO for fault detection based on drivability analysis.
Place a logic value, 1/0 or 0/1, depending on fault type and
number of inversions.
Justify the output value from PIs, considering all necessary
paths and adding backward time-frames.
If justification is impossible, then use drivability to select
another PO and repeat justification.
If the procedure fails for all reachable POs, then the fault is
untestable.
If 1/0 or 0/1 cannot be justified at any PO, but 1/X or 0/X can
be justified, the the fault is potentially detectable.
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Drivability Example
(11, 16)
(22, 17)
s-a-1
8
d(0/1) =
d(1/0) = 20
8
d(0/1) = 4
d(1/0) =
(4, 4)
(10, 16)
(17, 11)
d(0/1) = 9
d(1/0) =
8
(CC0, CC1)
= (6, 4)
(5, 9)
d(0/1) =
d(1/0) = 32
8
(10, 15)
FF
(6, 10)
d(0/1) = 120
d(1/0) = 27
8
d(0/1) = 109
d(1/0) =
CC0 and CC1 are SCOAP combinational controllabilities
d(0/1) and d(1/0) of a line are effort measures for driving
a specific fault effect to that line
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Complexity of ATPG
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Synchronous circuit -- All flip-flops controlled by clocks; PI and
PO synchronized with clock:
 Cycle-free circuit – No feedback among flip-flops: Test
generation for a fault needs no more than dseq + 1 timeframes, where dseq is the sequential depth.
 Cyclic circuit – Contains feedback among flip-flops: May
need 9Nff time-frames, where Nff is the number of flipflops.
Asynchronous circuit – Higher complexity!
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Smax
TimeFrame
max-1
TimeFrame
max-2
S3
Time- S2 Time- S1 Time- S0
Frame
Frame
Frame
-2
-1
0
max = Number of distinct vectors with 9-valued elements = 9Nff
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Cycle-Free Circuits
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Characterized by absence of cycles among flipflops and a sequential depth, dseq.
dseq is the maximum number of flip-flops on any
path between PI and PO.
Both good and faulty circuits are initializable.
Test sequence length for a fault is bounded by
dseq + 1.
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Cycle-Free Example
Circuit
F2
2
F3
F1
All faults are
testable in
this circuit.
3
Level = 1
F2
2
s - graph
F1
F3
Level = 1
3
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dseq = 3
13
Cyclic Circuit Example
Modulo-3 counter
Z
CNT
F2
F1
s - graph
F2
F1
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Modulo-3 Counter
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Cyclic structure – Sequential depth is undefined.
Circuit is not initializable. No tests can be
generated for any stuck-at fault.
After expanding the circuit to 9Nff = 81, or fewer,
time-frames ATPG program calls any given target
fault untestable.
Circuit can only be functionally tested by multiple
observations.
Functional tests, when simulated, give no fault
coverage.
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Adding Initializing Hardware
Initializable modulo-3 counter
Z
CNT
F2
F1
s-a-0
s-a-1
CLR
s-a-1
s-a-1
Untestable fault
Potentially detectable faults
s - graph
F1
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F2
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Benchmark Circuits
Circuit
PI
PO
FF
Gates
Structure
Seq. depth
Total faults
Detected faults
Potentially detected faults
Untestable faults
Abandoned faults
Fault coverage (%)
Fault efficiency (%)
Max. sequence length
Total test vectors
Gentest CPU s (Sparc 2)
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s1196
14
14
18
529
Cycle-free
4
1242
1239
0
3
0
99.8
100.0
3
313
10
s1238
14
14
18
508
Cycle-free
4
1355
1283
0
72
0
94.7
100.0
3
308
15
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s1488
8
19
6
653
Cyclic
-1486
1384
2
26
76
93.1
94.8
24
525
19941
s1494
8
19
6
647
Cyclic
-1506
1379
2
30
97
91.6
93.4
28
559
19183
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Asynchronous Circuit
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An asynchronous circuit contains unclocked memory
often realized by combinational feedback.
Almost impossible to build, let alone test, a large
asynchronous circuit.
Clock generators, signal synchronizers, flip-flops are
typical asynchronous circuits.
Many large synchronous systems contain small
portions of localized asynchronous circuitry.
Sequential circuit ATPG should be able to generate
tests for circuits with limited asynchronous parts,
even if it does not detect faults in those parts.
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Asynchronous Model
Synchronous PIs
CK
Combinational
Feedback Paths:
Feedback set
PPI
CK
Feedback-free
Combinational
Logic
C
Synchronous POs
System
Clock, CK
Clocked
Flip-flops
Fast model
Clock, FMCK
Feedback
delays
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PPO
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Modeling circuit is
Shown in orange.
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Time-Frame Expansion
Vector k
PI
Feedback
set
PPI
C
CK
PO
Time-frame
-k+1
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C
FMCK
C
FMCK
C
FMCK
Feedback
set
PPO
Asynchronous feedback
stabilization
Time-frame k
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Time-frame
-k-1
20
Asynchronous Example
0
0
1
1
s-a-0
s-a-0
s-a-0
1
X 1
1
0
X 0
0
1
0 1
1
s-a-0
s-a-0
s-a-0
1
0
1
0
Vectors
1 2 3 4
s-a-0
s-a-1
Outputs
1 2 3 4
Gentest results:
Faults: total 23, detected 15, untestable 8 (shown in red),
potentially detectable none
Vectors: 4
Sparc 2 CPU time: test generation 33ms, fault simulation 16ms
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Summary
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Combinational ATPG algorithms are extended:
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Cycle-free circuits:
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Require at most dseq + 1 time-frames
Always initializable
Cyclic circuits:
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Time-frame expansion unrolls time as combinational array
Nine-valued logic system
Justification via backward time
May need 9Nff time-frames
Circuit must be initializable
Partial scan can make circuit cycle-free (Chapter 14)
Asynchronous circuits:
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High complexity
Low coverage and unreliable tests
Simulation-based methods are more useful (Section 8.3)
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Exercise
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Which type of circuit is easier to test? Circle one in each:
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Combinational or sequential
Cyclic or cycle-free
Synchronous or asynchronous
What is the maximum number of input vectors that may be
needed to initialize a cycle-free circuit with k flip-flops?
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Answers to Exercise
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Which type of circuit is easier to test? Circle one in each:
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Combinational or sequential
Cyclic or cycle-free
Synchronous or asynchronous
What is the maximum number of input vectors that may
be needed to initialize a cycle-free circuit with k flip-flops?
k vectors. Because that is the maximum sequential
depth possible. An example is a k bit shift register.
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