Transcript Lecture 10: Combinational ATPG and Logic Redundancy

Lecture 10
Combinational ATPG and
Logic Redundancy


Redundancy identification
Redundancy removal
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 10
1
Irredundant Hardware
and Test Patterns

Combinational ATPG cannot always find redundant
(unnecessary) hardware

Fault
Test
a sa1, b sa0
A=1
a sa0, b sa1
A=0

Therefore, these faults are not redundant
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 10
2
Redundant Hardware
and Simplification
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 10
3
Redundant Fault q sa1
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 10
4
Multiple Fault Masking

Single fault f sa0 is tested by input vector 110.
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 10
5
Multiple Fault Masking

f sa0 is masked when fault q sa1 is also present.
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 10
6
Intentional Redundant
Implicant BC

Elimination of hazards in circuit output
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 10
7
Fault Cone and D-frontier


Fault Cone – Set of hardware affected by fault
D-frontier – Set of gates closest to POs with fault
effect(s) at input(s)
D-frontier
Fault Cone
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 10
8
Algorithm 7.1 (p. 171)
Redundancy Removal
Repeat until there are no redundant faults:
{
Use ATPG to find all redundant faults;
Remove all redundant faults with nonoverlapping fault cone areas;
}
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 10
9