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ELEC7250 VLSI Testing:
Final Project
Andrew White
4/27/2006
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Overview
Problem Description
Plan
Results
Demonstration
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Plan
Compiler
– Hierarchical bench formats are flattened
Logic Simulator
– Used simulation table and test vectors
– Two states (1,0)
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Plan
Algorithm
– Input vector is propogated through to the
output
– Traverse through the gates in levels
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Results
CPU Time vs. Number of Vectors
30
CPU Time (s)
25
20
15
10
5
0
10
210
410
610
810
1010
Vectors
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Results
CPU Time vs. Number of Gates
10000
Time (s)
1000
100
Sequential
10
1
6
506
1006
1506
2006
2506
0.1
Gates
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Plan
Due to long logic simulations
– Parallelize the problem
Parallel Approach
– Same algorithm as the sequential approach
– Main node broadcasts the simulation table to all other
nodes
– Main node reads in test vector file and evenly distributes
vectors to all other nodes
– Each node computes vector values and reports the
results to the main node
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Results
CPU Time vs. Number of Gates
14000
12000
Time (s)
10000
8000
Parallel (2 PE's)
Sequential
6000
4000
2000
0
6
162
1002
2416
Gates
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Fault Diagnosis
Find faulty vector
Find faulty outputs
Algorithm complexity
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Demonstration
C17 Circuit
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Conclusion
Questions/Comments?
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