Transcript Lecture 1

ELEC 5970-003/6970-003
Advanced Topics in Electrical Engineering
Designing VLSI for Low-Power and Self-Test
Fall 2004
Vishwani D. Agrawal
James J. Danaher Professor
Department of Electrical and Computer Engineering
Auburn University
http://www.eng.auburn.edu/~vagrawal
[email protected]
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Course Objective
• Low-power design and self-test are two of
the current needs in VLSI design.
• Learn basic concepts
• Gain hands-on experience in one of both
areas.
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Low-Power Design
• Design practices that reduce power
consumption at least by one order of
magnitude; in practice 50% reduction is
often acceptable.
• General topics
– High-level and software techniques
– Gate and circuit-level methods
– Power estimation techniques
– Test power
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VLSI Chip Power Density
Source: Intel
Sun’s
Surface
Power Density (W/cm2)
10000
Rocket
Nozzle
1000
Nuclear
Reactor
100
8086
10 4004
8008 8085
386
286
8080
1
1970
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Hot Plate
1980
P6
Pentium®
486
1990
Year
2000
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Specific Topics on Low-Power
•
•
•
•
•
Power dissipation in CMOS circuits
Low-power CMOS technologies
Dynamic reduction techniques
Leakage power
Power estimation
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Built-In Self-Test (BIST)
• Circuit includes hardware to test itself
• Learn basic concepts of digital BIST
• Project emphasis on mixed-signal BIST
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Power in a CMOS Gate
VDD
iDD(t)
Ground
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Power and Energy
• Instantaneous power (Watts)
P(t) = iDD(t) VDD
• Peak power (Watts)
Ppeak = Max {P(t)}
• Average power (Watts)
T
Pav = [ ∫0 P(t) dt ]/T
• Energy (Joules)
T
E = ∫0 P(t) dt
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Components of Power
• Dynamic
– Signal transitions
• Logic activity
• Glitches
– Short-circuit
• Static
– Leakage
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Power of a Transition
R
VDD
Power
= CVDD2/2
C
R
Ground
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Logic Activity and Glitches
1
2
3
6
5
4
d=2
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d=1
d=1
d=1
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Power Estimation Methods
• Spice: Accurate but expensive
• Logic-level
– Event-driven simulation
– Statistical
– Probabilistic
• High-level: Hierarchical
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Low-Power Design Techniques
• Circuit design methods
–Reduced supply voltage
–Adiabatic switching and charge recovery
–Logic design for reduced activity
–Reduced Glitches
–Transistor sizing
–Pass-transistor logic
–Pseudo-nMOS logic
–Multi-threshold gates
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Low-Power Design Techniques
• Functional and architectural methods
– Clock suppression
– Power down
– Algorithmic and Software methods
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Student Evalulation
• Homework (30%) – three
• Student presentation (10%)
• Research paper (30-60%) – a publishable
paper will exempt the student from the
final exam
• Final Exam (0-30%)
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