Transcript Lecture 14

ELEC 5970-001/6970-001(Fall 2005)
Special Topics in Electrical Engineering
Low-Power Design of Electronic Circuits
Low-Power Logic Families
Pass-Transistor Logic
Vishwani D. Agrawal
James J. Danaher Professor
Department of Electrical and Computer Engineering
Auburn University
http://www.eng.auburn.edu/~vagrawal
[email protected]
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Low-Power Logic Styles
•
•
•
•
•
•
Pass transistor logic
Dynamic logic
Domino logic
Adiabatic and charge recovery logic
Asynchronous logic
Logic restructuring
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Pass-Transistor Logic
• Requires fewer transistors
– Smaller area
– Reduced capacitance
– Reduced energy and power
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AND Gate
B
A
F = AB
0
Need 4 transistors instead of 6 for CMOS gate.
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Reduced Voltage Swing
IN
Vx = VDD – Vtn
OUT
VDD = 2.5V
n transistors, W/L = 0.5μ/0.25μ
p transistors, W/L = 1.5μ/0.25μ
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Spice Simulation
3.0
Voltage, V
IN
2.0
Vx
1.0
OUT
0.0
0
0.5
1.0
1.5
2.0
Time, ns
J. M. Rabaey, A. Chandrakasan and B. Nokolić, Digital Integrated
Circuits, Upper Saddle River, New Jersey: Pearson Education, 2003.
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Voltage Transfer Characteristic
(VTC) of AND Gate
B
A
F = AB
0
n transistors, W/L = 0.5μ/0.25μ
p transistors, W/L = 1.5μ/0.25μ
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VTC: Spice Simulation
3.0
IN
VDD – Vtn
F, V
2.0
B = VDD
A = 0 → VDD
1.0
A = VDD, B = 0 → VDD
A = B = 0 → VDD
OUT
0.0
0
0.5
1.0
1.5
2.0
2.5
Vin, V
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Energy If this voltage is insufficient
for turning the pMOS
Transistor in inverter off, leakage
power will be consumed.
0 → VDD
Vout
VDD = 2.5V
i(t)
E0→1
=
CL
T
∫ P(t) dt
0
VDD-Vtn
=
∫ CL dVout
0
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T
= VDD ∫ i(t) dt
0
= CL VDD (VDD – Vtn)
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Ways to Reduce Leakage
• Level restoration
• Multiple-threshold transistors
• Transmission-gate logic
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Level Restoration
VDD
Level
restorer
B
Vout
A
CL
Switching threshold
= VDD/2
Level restorer device should be weaker than the nMOS
pass transistor. Otherwise, VDD → 0 transition at Vout
will be impossible.
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Multiple-Threshold Transistors
• Use zero-threshold pass-transistors.
• Use high-threshold transistors in all other
gates.
• This can cause leakage through multiple
gates.
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Leakage Through Zero-Threshold
Transistors
1
Zero or low-threshold
transistors
0
Leakage current path 0
1
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Transmission-Gate Logic
• Provides both power and ground levels.
• Good design, except needs more
transistors.
A
Inverting multiplexer
S’A’ + SB’
S
B
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Transmission-Gate XOR
B
AB’+A’B
A
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Synthesis of PTL
Shannon’s expansion:
Z
B
=
=
=
=
1
C
C
0
1
0
1
0
A
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AB + BC + AC
A(B+BC+C) + A’(BC)
A(B+C) + A’BC
A[B+B’C] + A’[BC]
1
0
Z
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A
B
C
Z
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
0
1
0
1
1
1
1
0
1
1
1
1
1
16
Pass-Transistor Cell
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Synthesis of Z = A’B’ + BC’ + A’C
A
0
B
C
Z
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Synthesis of Z = A’ + BC’ + B’C
C
C’
0
B
B’
A
A’
Z
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Synthesis of Z = AB’C’ + A’B’C
C’
C
1
B
B’
A’
A
Z
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CPL: Complementary PassTransistor Logic
• Every signal and its complement is
generated.
• Gates are static, because the output is
connected to either VDD or GND.
• Design is modular; same cell can produce
various gates by simply permuting the
input signals.
• Also called differential pass-transistor logic
(DPL)
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A CPL Cell
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CPL Cell Used As AND/NAND
B
B’
A
Z = AB
B
A’
Z=(AB)’
B’
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CPL Cell Used As OR/NOR
B’
B
A
Z = A+B
B
A’
Z=(A+B)’
B’
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CPL Cell Used As XOR/XNOR
B’
B
A
Z = AB’+A’B
A’
A’
Z= AB+A’B’
A
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References
• G. R. Cho and T. Chen, “On the Impact of
Technology Scaling on Mixed PTL/Static
Logic,” Proc. IEEE Int. Conf. Computer
Design, 2002.
• R. Zimmermann and W. Fichtner, “LowPower Logic Styles: CMOS Versus PassTransistor Logic,” IEEE J. Solid State
Circuits, vol. 32, no. 7, pp. 1079-1090, July
1997.
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