Transcript Lecture 6

ELEC 5970-001/6970-001(Fall 2005)
Special Topics in Electrical Engineering
Low-Power Design of Electronic Circuits
Dynamic Power
Vishwani D. Agrawal
James J. Danaher Professor
Department of Electrical and Computer Engineering
Auburn University
http://www.eng.auburn.edu/~vagrawal
[email protected]
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CMOS Dynamic Power
Dynamic Power
=
Σ 0.5 αi fclk CLi VDD2
All gates i
≈ 0.5 α fclk CL VDD2
≈ α01 fclk CL VDD2
where
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α
α01
fclk
CL
VDD
average gate activity factor
= 0.5α, average 0→1 trans.
clock frequency
total load capacitance
supply voltage
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Example: 0.25μm CMOS Chip
•
•
•
•
•
f = 500MHz
Average capacitance = 15fF/gate
VDD = 2.5V
106 gates
Power = α01 f CL VDD2
= α01×500×106×(15×10-15×106) ×2.52
= 46.9W, for α01 = 1.0
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Signal Activity, α
T=1/f
α01= 1.0
Clock
α01=
0.5
Comb.
signals
α01= 0.5
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Reducing Dynamic Power
• Dynamic power reduction is
– Quadratic with reduction of supply voltage
– Linear with reduction of capacitance
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2.5
0
2.0
-4
Gain
Vout (V)
0.25μm CMOS Inverter, VDD=2.5V
1.5
1.0
-8
-12
0.5
-16
0
-20
0
0
0.5
1.0
1.5
2.0
2.5
Vin (V)
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0.5
1.0
1.5
2.0
2.5
Vin (V)
6
0.25μm CMOS Inverter, VDD< 2.5V
2.5
0.2
Vout (V)
Vout (V)
2.0
1.5
1.0
0.1
0.05
0.5
0
0
0
0.5
1.0
1.5
2.0
Vin (V)
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0.15
2.5
0
Gain = -1
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0.1
0.15
0.2
Vin (V)
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Lower Bound on VDD
• For proper operation of gate, maximum gain (for
Vin = VDD/2) should be greater than 1.
• Gainmax = -(1/n)[exp(VDD /2ΦT) – 1] = -1
• n = 1.5
• ΦT = kT/q = 26mV
• VDD = 48V
• VDDmin > 2 to 4 times kT/q or ~100mV at room
temperature (27oC)
• Ref.: J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital
Integrated Circuits, Upper Saddle River, New Jersey: Pearson
Education, 2003.
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Impact of VDD on Performance
Inverter delay
=
CLVDD
K ───────
(VDD – Vt )α
Delay (ns)
40
30
20
Power
10
Delay
0
0.6V
VDD=Vt
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1.8V
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3.0V
VDD
9
Optimum Power × Delay
Power × Delay, PD =
VDD3
constant × ───────
(VDD – Vt)α
For minimum power-delay product, d(PD)/dVDD = 0
VDD
=
3Vt
───
3–α
For long channel devices, α = 2, VDD = 3Vt
For very short channel devices, α = 1, VDD = 1.5Vt
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Transistor Sizing for Performance
• Problem: If we increase W/L to make the
charging or discharging of load
capacitance, then the increased W
increases the load for the driving gate
Cin
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CL
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Fixed-Taper Buffer
Delay
= t0
Vin
1
Cin
α
α2
αi-1
Ci = αi-1Cin
CL = αnCin
αn-1
Vout
CL
Ref.: J. Segura and C. F. Hawkins, CMOS Electronics, How It Works,
How It Fails, Piscataway, New Jersey: IEEE Press, 2004.
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Buffer (Cont.)
αn
n
=
CL/Cin
=
ln (CL/Cin)
──────
ln α
ith stage delay, ti = αt0, i = 1, . . . n,
because each stage drives a stage α times
bigger than itself.
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Buffer (Cont.)
Total delay
=
n
Σ ti =
i=1
nαt0
= ln(CL/Cin) αt0/ln(α)
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Buffer (Cont.)
Differentiating total delay with respect to
α and equating to 0, we get
αopt = e ≈ 2.7
The optimum number of stages is
nopt = ln(CL/Cin)
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Further Reading
B. S. Cherkauer and E. G. Friedman, “A Unified Design
Methodology for CMOS Tapered Buffers,” IEEE Trans.
VLSI Systems, vol. 3, no. 1, pp. 99-111, March 1995.
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