Transcript Lecture 3

ELEC 5970-001/6970-001(Fall 2005)
Special Topics in Electrical Engineering
Low-Power Design of Electronic Circuits
Capacitance in a CMOS Circuit
Vishwani D. Agrawal
James J. Danaher Professor
Department of Electrical and Computer Engineering
Auburn University
http://www.eng.auburn.edu/~vagrawal
[email protected]
8/30/05
ELEC5970-001/6970-001 Lecture 3
1
Capacitances
VDD
C1
In
Out
C2
CW
GND
8/30/05
ELEC5970-001/6970-001 Lecture 3
2
Miller Capacitance
VDD
C1
In
Out
CM
C2
CW
GND
8/30/05
ELEC5970-001/6970-001 Lecture 3
3
Before Transition
VDD
C1
In
0 +VDD
CM
Out
C2
CW
GND
8/30/05
ELEC5970-001/6970-001 Lecture 3
4
After Transition
VDD
-VDD
In
2
Energy from supply = 2 CM VDD
Effective capacitance = 2 CM
C1
0
Out
CM
C2
CW
GND
8/30/05
ELEC5970-001/6970-001 Lecture 3
5
Capacitances in MOSFET
Cgs
Cgd
Gate
Gate oxide
Source
Drain
Cg
Cs
8/30/05
Bulk
Cd
ELEC5970-001/6970-001 Lecture 3
6
Bulk nMOSFET
Polysilicon
Gate
Drain
W
Source
n+
n+
L
p-type body (bulk)
SiO2
Thickness = tox
8/30/05
ELEC5970-001/6970-001 Lecture 3
7
Gate Capacitance
Cg
=
Cox WL = C0, intrinsic cap.
Cg
=
Cpermicron W
Cpermicron =
where εox
εox
Cox L
=
── L
tox
= 3.9ε0 for Silicon dioxide
= 3.9×8.85×10-14 F/cm
8/30/05
ELEC5970-001/6970-001 Lecture 3
8
Intrinsic Capacitances
Region of operation
Capacitance
Cutoff
Linear
Saturation
Cgb
C0
0
0
Cgs
0
C0 /2
2/3 C0
Cgd
0
C0 /2
0
Cg =
Cgs+Cgd+Cgb
C0
C0
2/3 C0
Weste and Harris, CMOS VLSI Design, Addison-Wesley, 2005, p. 78.
8/30/05
ELEC5970-001/6970-001 Lecture 3
9
Low-Power Transistors
• Device scaling to reduce capacitance and
voltage.
• Body bias to reduce threshold voltage and
leakage.
• Multiple threshold CMOS (MTCMOS).
• Silicon on insulator (SOI)
8/30/05
ELEC5970-001/6970-001 Lecture 3
10
Device Scaling
• Reduced dimensions
– Reduce supply voltage
– Reduce capacitances
– Reduce delay
– Increase leakage due to reduced VDD/ Vt
8/30/05
ELEC5970-001/6970-001 Lecture 3
11
Optimum Threshold Voltage
Vt = 0.7V
Vt = 0.3V
Delay
Delay or
Energy-delay
product
Energy-delay product
0
1
2
3
4
5
6
VDD / Vt
8/30/05
ELEC5970-001/6970-001 Lecture 3
12
Bulk CMOS Inverter
Polysilicon (input)
SiO2
Output
metal 1
GND
p+
n+
n+
VDD
p+
p+
n+
n-well
p-substrate (bulk)
8/30/05
ELEC5970-001/6970-001 Lecture 3
13