Transcript Lecture 1

ELEC 5970-001/6970-001 (Fall 2005)
Special Topics in Electrical Engineering
Low-Power Design of Electronic Circuits
Introduction
Vishwani D. Agrawal
James J. Danaher Professor
Department of Electrical and Computer Engineering
Auburn University
http://www.eng.auburn.edu/~vagrawal
[email protected]
8/18/05
ELEC 5970-001/6970-001 Lecture 1
1
Course Objective
• Low-power is a current need in VLSI
design.
• Learn basic ideas, concepts and methods.
• Gain hands-on experience.
8/18/05
ELEC 5970-001/6970-001 Lecture 1
2
Low-Power Design
• Design practices that reduce power
consumption at least by one order of magnitude;
in practice 50% reduction is often acceptable.
• General topics
–
–
–
–
–
8/18/05
Algorithms and architectures
High-level and software techniques
Gate and circuit-level methods
Power estimation techniques
Test power
ELEC 5970-001/6970-001 Lecture 1
3
VLSI Chip Power Density
Source: Intel
Sun’s
Surface
Power Density (W/cm2)
10000
Rocket
Nozzle
1000
100
8086
Hot Plate
10 4004
8008 8085
386
286
8080
1
1970
8/18/05
Nuclear
Reactor
1980
P6
Pentium®
486
1990
Year
2000
ELEC 5970-001/6970-001 Lecture 1
2010
4
Specific Topics on Low-Power
• Power dissipation in CMOS circuits
• Device technology
– Low-power CMOS technologies
– Energy recovery methods
• Circuit and gate level methods
– Logic synthesis
– Dynamic power reduction techniques
– Leakage power reduction
• System level methods
– Microprocessors
– Arithmetic circuits
– Low power memory technology
• Test Power
• Power estimation
8/18/05
ELEC 5970-001/6970-001 Lecture 1
5
Power in a CMOS Gate
VDD
iDD(t)
Ground
8/18/05
ELEC 5970-001/6970-001 Lecture 1
6
Power Dissipation in
CMOS Logic (0.25µ)
Ptotal (0→1) = CL VDD2 + tscVDD Ipeak + VDDIleakage
CL
%75
8/18/05
ELEC 5970-001/6970-001 Lecture 1
%20
%5
7
Power and Energy
• Instantaneous power (Watts)
P(t) = iDD(t) VDD
• Peak power (Watts)
Ppeak = Max {P(t)}
• Average power (Watts)
T
Pav = [ ∫0 P(t) dt ]/T
• Energy (Joules)
T
E = ∫0 P(t) dt
8/18/05
ELEC 5970-001/6970-001 Lecture 1
8
Components of Power
• Dynamic
– Signal transitions
• Logic activity
• Glitches
– Short-circuit
• Static
– Leakage
8/18/05
ELEC 5970-001/6970-001 Lecture 1
9
Power of a Transition
R
VDD
Power
= CVDD2/2
C
R
Ground
8/18/05
ELEC 5970-001/6970-001 Lecture 1
10
Logic Activity and Glitches
1
2
3
6
d=2
8/18/05
5
4
7
d=1
d=1
d=1
ELEC 5970-001/6970-001 Lecture 1
11
Low-Power Design Techniques
• Circuit and gate level methods
–Reduced supply voltage
–Adiabatic switching and charge recovery
–Logic design for reduced activity
–Reduced Glitches
–Transistor sizing
–Pass-transistor logic
–Pseudo-nMOS logic
–Multi-threshold gates
8/18/05
ELEC 5970-001/6970-001 Lecture 1
12
Low-Power Design Techniques
• Functional and architectural methods
– Clock suppression
– Clock frequency reduction
– Supply voltage reduction
– Power down
– Algorithmic and Software methods
8/18/05
ELEC 5970-001/6970-001 Lecture 1
13
Test Power
• Power grid on a VLSI chip is designed for
certain current capacity during functional
operation:
– Average current → heat dissipation
– Peak current → noise, ground bounce
• Problem – Tests like scan or BIST are
nonfunctional and may cause higher than
the functional circuit activity; a functionally
good chip can fail the test.
8/18/05
ELEC 5970-001/6970-001 Lecture 1
14
Power Estimation Methods
• Spice: Accurate but expensive
• Logic-level
– Event-driven simulation
– Statistical
– Probabilistic
• High-level: Hierarchical
8/18/05
ELEC 5970-001/6970-001 Lecture 1
15
Student Evaluation
•
•
•
•
8/18/05
Homework (30%) – almost 1/week
Class Project (30%)
Student presentation (10%)
Final Exam (30%)
ELEC 5970-001/6970-001 Lecture 1
16