Lecture 15: Technology Mapping
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Transcript Lecture 15: Technology Mapping
ELEC 7770
Advanced VLSI Design
Spring 2016
Technology Mapping
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University
Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr16
Spring 16, Apr 18 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
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Logic Synthesis
Definition: To design a logic circuit such that it
meets the specifications and can be
economically manufactured:
Performance – meets delay specification, or has
minimum delay.
Cost – uses minimum hardware, smallest chip
area, smallest number of gates or transistors.
Power – meets power specification, or consumes
minimum power.
Testablility – has no redundant (untestable) logic
and is easily testable.
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References on Synthesis
G. De Micheli, Synthesis and Optimization of
Digital Circuits, New York: McGraw-Hill, 1994.
S. Devadas, A. Ghosh and K. Keutzer, Logic
Synthesis, New York: McGraw-Hill, 1994.
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Synthesis: A Two-Step Process
Minimization – Obtain MSOP or MPOS. This is
also known as two-level minimization because
the result can be implemented as a two-level
AND-OR or NAND-NAND or NOR-NOR circuit.
Technology mapping – Considering design
requirements, transform the minimized form into
one of the technologically realizable forms:
Spring 16, Apr 18 . . .
Programmable logic array (PLA)
Standard cell library
Field programmable gate array (FPGA)
Other . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
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Programmable Logic Array (PLA)
A direct implementation of multi-output function
as a two-level circuit in MOS technology.
PLA styles:
NAND-NAND
NOR-NOR
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Example: Two-Output Function
Need four products: P1, P2, P3, P4
A
F1
0
4
12
A
F2
8
0
4
12
8
1
1
5
1
3
C
13
1
7
1
15
1
2
6
9
1
13
1
11
1
14
5
10
9
1
D
3
C
7
15
1
2
6
1
14
1
D
11
1
10
1
B
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B
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Two-Level AND-OR Implementation
Also known as technology-independent circuit.
INPUTS
C
AND
OR
P1
F1
P2
A
P3
B
F2
P4
D
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NAND-NAND Implementation
INPUTS
C
NAND
NAND
P1
F1
P2
A
P3
B
D
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F2
P4
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A NAND Gate in nMOS Technology
VDD
VDD
Depletion
load
XY
VDD
Enhancement
load
XY
XY
X
X
X
Y
Y
Y
GND
GND
GND
R. C. Jaeger and T, N. Blalock, Microelectronic Circuit Design,
Boston: McGraw-Hill, 2008, Section 6.8.2.
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NAND-NAND PLA
A
B
C
D
F1
F2
VDD
VDD
P1
VDD
P2
VDD
P3
VDD
P4
VDD
GND
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NAND-NAND PLA SCHEMATIC
C
D
F1
F2
OUTPUTS
B
INPUTS
A
Transistors at
cross-points
P1
P2
P3
P4
AND-plane
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ELEC 7770: Advanced VLSI Design (Agrawal)
OR-plane
11
Standard-Cell Design
Obtain two-level minimized form.
Map the design onto predesigned building blocks
called standard cells (technology mapping).
Standard-cell library contains predesigned logic
cells in the technology of manufacture. Examples
of technology:
90 nanometer CMOS
65 nanometer CMOS
45 nanometer CMOS
...
This is known as application-specific integrated
circuit (ASIC).
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Technology Mapping
Find a common logic element, e.g., two-input
NAND gate or inverter (one-input NAND).
MSOP is converted into NAND-NAND circuit.
Split larger input gates into two-input NAND gates
and inverters.
Cover the circuit with standard cells, also split into
two-input NAND gates and inverters (graphmatching).
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A Typical Cell Library
Name
Area units (cost)
Inputs
Inverter
2
A
NAND2
3
A, B
NAND3
4
A, B, C
NAND4
5
A, B, C, D
AOI21
4
A, B, C
OAI21
4
A, B, C
AOI22
5
A, B, C, D
XOR
4
A, B
Output function, Z
ZA
Z AB
Z ABC
Z ABCD
Z AB C
Z ( A B)C
Z AB CD
Z AB AB
S. Devadas, A. Ghosh and K. Keutzer, Logic Synthesis, New York: McGraw-Hill
1994, Section 7.7, pp. 185-198.
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NAND3 Cell in Transistors
VDD
Z
A
B
C
GND
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NAND3 Cell Graphs
Directed Acyclic
Graph (DAG)
(tree)
Root ≡ Output
One-input
node (NOT)
Two-input
node (NAND)
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NAND4 Cell
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AOI21 Cell
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OAI21 Cell
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AOI22 Cell in Transistors
VDD
Pull-up network
A
Z
B
C
Pull-down network
D
GND
Observe that in a CMOS circuit, any vector of input variables connects the output Z
either to GND or to VDD, giving it a value 0 or 1, respectively. Examining the pull-down
network, we notice that the output is connected to GND if AB = 1 or CD =1. That
gives the output function as, Z AB CD . The cell, therefore, is AOI22.
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AOI22 Cell
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XOR Cell
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NAND Graphs for Library Cells
Name
Area units (cost)
Inputs
Inverter
2
A
NAND2
3
A, B
NAND3
4
A, B, C
NAND4
5
A, B, C, D
AOI21
4
A, B, C
OAI21
4
A, B, C
AOI22
5
A, B, C, D
XOR
4
A, B
Spring 16, Apr 18 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
NAND graph
23
Technology Mapping Procedure
Obtain MSOP.
Convert to two-level AND-OR circuit.
Transform to two-level NAND-NAND circuit.
Transform to two-input NAND and inverter tree
network.
Perform an optimal pattern matching to obtain a
minimum cost tree covering.
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Previous Example: 2-Level NAND
(Slide 8)
INPUTS
C
NAND
NAND
P1
F1
P2
A
P3
B
D
Spring 16, Apr 18 . . .
F2
P4
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A Simple Technology Mapping
NAND2 (3)
C
NAND2 (3)
(2)
F1
D
NAND3 (4)
B
P2
(2)
NAND3 (4)
F2
NAND2 (3)
A
Cost = 24
NAND2 (3)
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Optimum Mapping: Convert NAND
Circuit to Directed Acyclic Graph (DAG)
C
P1
F1
A
P2
P3
B
D
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P4
ELEC 7770: Advanced VLSI Design (Agrawal)
F2
Each node is a
NAND gate.
(NOT ≡ 1-input NAND)
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Split DAG into Trees (Forest)
C
D
F1
C
B
D
P2
P2
A
P2
B
A
F2
D
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Cost = 24
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Split Nodes With More Than Two Branches
(Use NAND3, NAND4 Graphs)
≡
P2 or F2
≡
P2 or F2
or
NAND4
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Uniform Branching (1 or 2)
C
D
P2
F1
B
D
C
P2
P2
A
F2
B
A
D
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Cost = 32
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Graph Matching
C
OAI21 (4)
(2)
D
F1
Nodes inserted
For pattern matching
P2
B
NAND3 (4)
C
P2
D
P2
NAND2 (3)
A
NAND3 (4)
F2
B
(2)
A
D
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NAND2 (3)
ELEC 7770: Advanced VLSI Design (Agrawal)
Cost = 22
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Technology Mapping
C
D
(2)
OAI21 (4)
(2)
P2
Inverters
inserted
For pattern
B
matching
F1
NAND3 (4)
C
D
P2
P2
NAND3 (4)
A
B
F2
(2)
A
D
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NAND2 (3)
Cost = 22
NAND2 (3)
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Mapped Circuit
C
AOI21 (4)
(2)
D
NAND3 (4)
B
F1
P2
(2)
NAND3 (4)
F2
NAND2 (3)
A
Cost = 22
NAND2 (3)
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Original Reference
K. Keutzer, “DAGON: Technology Binding and
Local Optimization by DAG matching,” Proc.
24th Design Automation Conf., 1987, pp. 341347.
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