Transcript Lecture 7: Constraint Graph and Retiming Solution

ELEC 7770
Advanced VLSI Design
Spring 2016
Constraint Graph and Retiming Solution
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University
Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr16/course.html
Spring 2016, Feb 17 . . .
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Retiming Theorem
 Given a network G(V, E, W) and a cycle time T,
(r1, . . . ) is a feasible retiming if and only if:
 ri – rj ≤ wij
for all edges (vi,vj) ε E
 ri – rj ≤ W(vi,vj) – 1 for all node-pairs vi, vj such that
D(vi,vj) > T
Where,
W(vi,vj) is the minimum weight path between vi and vj
D(vi,vj) is the maximum delay among all minimum
weight paths between vi and vj
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Retiming Theorem Explained
 Condition 1, ri – rj ≤ wij, is related to edge weight:
 Original circuit is feasible  original weight wij is positive
 Originally, ri = rj = 0
 Retiming, ri ≠ 0, rj ≠ 0 → rj flip-flops added to eij, ri flipflops removed from eij, net reduction ri – rj must be less
than wij to leave the retimed weight of eij positive.
0 → rj
0 → ri
vi
wij – ri + rj ≥ 0
vj
 Condition 2, ri – rj ≤ W(vi,vj) – 1 is related to path
delays between node pair (vi, vj) being less than
clock period T whenever path weight is 0.
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Examine Condition 2
W1, D1
rj
ri
vi
W2, D2
vj
W3, D3
W1 = W2 < W3, W(vi, vj) = W1 = W2, minimum weight among paths
D1 > D2, therefore D(vi, vj) = D1, maximum delay of a minimum weight path
If D1 ≤ T, there is no requirement on ri, rj
If D1 > T, Retimed weight W1’ = W1 – ri + rj ≥ 1 (at least 1 FF on path)
or ri – rj ≤ W1 – 1
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Timing Optimization
 Find the clock period (T) by path analysis.
 Set clock period to T/2 and find a feasible




retiming.
If feasible, further reduce the clock period to
half.
If not feasible, increase clock period.
Do a binary search for optimum clock period.
Retime the circuit.
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Representing a Constraint
ri – rj ≤ wij
rj
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or
– wij
rj ≥ ri – wij
ri
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Constraint Graph
-6
r1 ≥ r0 + 3
r1 ≥ r2 + 1
r2 ≥ r0 + 1
r2 ≥ r1 – 1
r3 ≥ r1 + 1
r3 ≥ r2 + 4
r0 ≥ r3 – 6
r1
3
1
-1
r0
1
1
r3
4
r2
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Feasibility Condition
 A set of values for variables can be found if and

only if the constraint graph has no positive
cycles.
This is also the condition for the solvability of the
longest path problem, which provides a solution
to the set of constraints.
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Example: Infeasible Constraints
x2
x1 ≥ x2 + 6
x2 ≥ x1 – 3
x2 ≥ x1 – 3
6
x1
3
x2
-3
Positive cycle mean no
longest path can be found.
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x1 ≥ x2 + 6
0
3
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6
x1
9
Solving a Constraint Set
-6
r1 ≥ r0 + 3
r1 ≥ r2 + 1
r2 ≥ r0 + 1
r2 ≥ r1 – 1
r3 ≥ r1 + 1
r3 ≥ r2 + 4
r0 ≥ r3 – 6
r1
3
r0
Longest paths from source r0
1
r0, r1, r2, r3
Path lengths: s0=0, s1=3, s2=2, s3=6
Solution: r0=0, r1=3, r2=2, r3=6
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1
-1
1
r3
4
r2
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The General Path Problem
 Find the shortest (or longest) path in a graph

from a source vertex to all other vertices.
Graph has vertices and directed edges:
 Edge weights can be positive or negative
 Graph can be cyclic
 Single source vertex – a vertex with 0 in-degree (not
a necessary condition)
 Inconsistent problems
 Negative weight cycles for shortest path
 Positive weight cycles for longest path
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Dijkstra’s Shortest Path Algorithm
 Greedy algorithm.
 Applies to directed acyclic graphs (DAG) with positive


edge weights.
Computational complexity
O(|E| + |V| log |V|) ≤ O(n2)
References:
 A. Aho, J. Hopcroft and J. Ullman, Data Structures and
Algorithms, Reading, Massachusetts: Addison-Wesley, 1983.
 T. Cormen, C. Leiserson and R. Rivest, Introduction to
Algorithms, New York: McGraw-Hill, 1990.
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Dijkstra’s Shortest Path Algorithm
Example 1
w01=15
v0
source
v1
3
s0
s1
s2
s3
Initially: mark v0
0
15
2

Step 1: mark v2
0
12
2
8
Step 2: mark v3
0
11
2
8
Step 3: mark v1
0
11
2
8
v3
10
2
Alg. steps
6
v2
si = path weight (v0, vi)
Each step marks the path with smallest weight and updates the unmarked
path weights.
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Dijkstra’s Shortest Path Algorithm
Example 2
w01=15
v0
source
v1
3
s0
s1
s2
s3
Initially: mark v0
0
15
2

Step 1: mark v2
0
8
2
12
Step 2: mark v1
0
8
2
12
Step 3: mark v3
0
8
2
12
v3
6
2
Alg. steps
10
v2
si = path weight (v0, vi)
Each step marks the path with smallest weight and updates the unmarked
path weights.
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Dijkstra’s Algorithm, G(V, E, W)
s0(1) = 0
for ( i = 1 to n )
initialize source
initialize path weights, n=|V| –1
si(1) = w0i
repeat {
Select an unmarked vertex vq such that sq is minimal
Mark vq
foreach ( unmarked vertex vi )
si =
min
{ si, sq + wqi }
}
until (all vertices are marked)
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Try Dijkstra’s Algorithm for Your Graph
http://www.dgp.toronto.edu/people/JamesStewart/270/9798s/Laffra/DijkstraApplet.html
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Dijkstra’s Longest Path Algorithm
w01=15
v0
source
v1
3
v3
10
2
Either change min to max
Or change all positive weights to negatives
6
Alg. steps
s0
s1
s2
s3
Initially
0
-15 -2

Step 1: mark v1
0
-15 -2

Step 2: mark v2
0
-15 -2
-8
Step 3: mark v3
0
-15 -2
-8
v2
w01= -15
v0
source
v1
-3
v3
-10
-2
-6
v2
si = path length (v0, vi)
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Dijkstra’s Alg. Does Not Work for
Cycles, Mixed Weights
-2
w01=15
v0
source
v1
3
s0
s1
s2
s3
Initially: mark v0
0
15
2

Step 1: mark v2
0
7
2
6
Step 2: mark v3
0
7
2
6
Step 3: mark v1
0
7
2
6?
v3
5
2
Alg. steps
4
v2
si = path weight (v0, vi)
Algorithm stops because all vertices are marked.
But, there exists a v0 to v3 path of length 5
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Bellman’s Equations – Shortest Path
vj
vk
wki
wji
For all vertices:
vi
vm
wmi
si
wni
=
min
(sq + wqi)
vq ε pred(vi)
vn
sq =
minimum path weight between
source and vq
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Bellman-Ford Algorithm, G(V, E, W)
Bellman-Ford {
s0(1) = 0
for ( i = 1 to n )
initialize source
initialize path weights, n = |V| – 1
si(1) = w0i
for ( j = 1 to n )
n iterations
for ( i = 1 to n )
si(j+1) =
n nodes
min
{ si(j), sk(j) + wki }
vk ε pred(vi)
}
if ( si(j+1) == si(j) i ) return (true)
}
return (false)
Spring 2016, Feb 17 . . .
Complexity = O(|V||E|) ≤ O(n3)
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Bellman-Ford Shortest Path
n=3
w01=15
v0
source
v1
3
s1
s2
s3
Initially
0
15
2

Iteration 1
0
12
2
8
Iteration 2
0
11
2
8
Iteration 3
0
11
2
8
6
v2
si = path weight (v0, vi)
Spring 2016, Feb 17 . . .
s0
v3
10
2
Alg. steps
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Bellman-Ford Longest Path
Reverse the sign of weights and solve shortest path problem.
(Alternative: keep original weights and change min operator in
algorithm to max.)
n = 3 (shortest path)
Weights reversed
w01= -15
v0
source
v1
s0
s1
s2
s3
Initially
0
-15 -2

Iteration 1
0
-15 -2
-8
Iteration 2
0
-15 -2
-8
-3
v3
-10
-2
Alg. steps
-6
v2
si = path weight (v0, vi)
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Bellman’s Equations – Longest Path
vj
vk
wki
wji
For all vertices:
vi
vm
wmi
si
wni
=
max
(sq + wqi)
vq ε pred(vi)
vn
sq =
maximum path weight between
source and vq
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Bellman-Ford for Cycles, Neg. Weights
w01=15
v0
source
v1
-2
3
Alg. steps
s0
s1
s2
s3
Initially
0
15
2

Iteration 1
0
7
2
6
Iteration 2
0
7
2
5
Iteration 3
0
7
2
5
v3
5
2
n = 3 (shortest path)
4
v2
si = path weight (v0, vi)
This was incorrect with Dijkstra’s shortest path algorithm
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Bellman-Ford for Negative Cycle
w01=15
v0
source
v1
-3
Alg. steps
s0
s1
s2
s3
Initially
0
15
2

Iteration 1
0
7
2
6
Iteration 2
0
3
2
6
Iteration 3
0
3
2
5
v3
5
2
n = 3 (shortest path)
2
4
v2
si = path weight (v0, vi)
Values not stabilized after n iterations.
Inconsistent problem: negative cycle.
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Retiming Optimization
 Given circuit,
 Retiming variables initialized, ri = 0 for all i
 All edge weights, wij ≥ 0 (feasible circuit)
 Critical path delay, T
 Retiming optimization,
 Find {ri}, such that in retimed circuit
 New edge weights, wij’ ≥ 0 (feasible circuit)
 T minimized
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Retiming Example
10
a
5
b
FF
5
c
Delay
• Objective: Retime the circuit for smallest critical
path delay (Clock period, T).
• Find T and set T→ T/2 for binary search.
• Use retiming theorem
•
•
•
•
Condition 1 leads to original constraint graph.
Condition 2 adds clock constraints to graph.
Positive cycle no legal retiming, increase T.
Or, reduce T.
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Retiming Theorem
 Given a network G(V, E, W) and a cycle time T,
(r1, . . . ) is a feasible retiming if and only if:
 Condition 1: ri – rj ≤ wij
for all edges (vi,vj) ε E
 Condition 2: ri – rj ≤ W(vi,vj) – 1, for all node-pairs
vi, vj for which D(vi,vj) > T
Where,
W(vi,vj) is the minimum weight path between vi and vj
D(vi,vj) is the maximum delay among all minimum
weight paths between vi and vj
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Retiming Graph
a
10
b
5
FF
5
c
1
h
0
0
a
10
0
b
5
1
c
5
Critical path T = 15
It is the longest path consisting only of zero weight edges.
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Feasibility Constraints (Condition 1)
a
10
b
5
FF
5
1
c
Retiming Graph
rb FFs
h
0
0
a
10
0
b
5
1
c
5
rc FFs
ri – rj ≤ wij
 edges i → j
Retiming should not cause
negative edge weights.
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rh – ra ≤ 0
ra – rb ≤ 0
rb – rc ≤ 1
rc – rh ≤ 1
30
Constraint Graph
10
a
5
b
FF
5
c
-1
rh
-0
ra
-0
rb
-1
rc
rh – ra ≤ 0  rh – 0 ≤ ra
ra – rb ≤ 0  ra – 0 ≤ rb
Constraints for
rb – rc ≤ 1  rb – 1 ≤ rc
Condition 1
rc – rh ≤ 1  rc – 1 ≤ rh
Observation: Constraint graph has the same structure as the original
retiming graph, with signs of weights reversed. Vertex labels are the
retiming integer variables.
ri – rj ≤ wij
 edges i → j
Retiming should not cause
negative edge weights.
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Max Delay for Min Weight Paths
Retiming Graph
1
h
0
0
a
10
0
b
5
1
c
5
T = 15
W(h,a) = 0
W(h,b) = 0
W(h,c) = 1
W(a,b) = 0
W(a,c) = 1
W(a,h) = 2
D(h,a) = 10
D(h,b) = 15
D(h,c) = 20
D(a,b) = 15
D(a,c) = 20
D(a,h) = 20
W(b,c) = 1
W(b,h) = 2
W(b,a) = 2
W(c,h) = 1
W(c,a) = 1
W(c,b) = 1
D(b,c) = 10
D(b,h) = 10
D(b,a) = 20
D(c,h) = 5
D(c,a) = 15
D(c,b) = 20
W(x,y): minimum weight of x to y path
D(x,y): maximum delay of paths with weight W(x,y)
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Retime for T = 7.5?
Constraint graph
(feasibility)
-1
rh
-0
ra
-0
rb
-1
rc
Add constraints for critical path requirement
Condition 2:
ri – rj ≤ W(I,j) – 1
 paths (i,j) with D(i,j) > 7.5
W(h,a) = 0
W(h,b) = 0
W(h,c) = 1
W(a,b) = 0
W(a,c) = 1
W(a,h) = 2
Spring 2016, Feb 17 . . .
D(h,a) = 10
D(h,b) = 15
D(h,c) = 20
D(a,b) = 15
D(a,c) = 20
D(a,h) = 20
W(b,c) = 1
W(b,h) = 2
W(b,a) = 2
W(c,h) = 1
W(c,a) = 1
W(c,b) = 1
ELEC 7770: Advanced VLSI Design (Agrawal)
D(b,c) = 10
D(b,h) = 10
D(b,a) = 20
D(c,h) = 5
D(c,a) = 15
D(c,b) = 20
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Timing Optimization, T = 7.5?
15
-1
0
1
1
1
rh
0
ra
-1
-1
0
W(h,a) = 0
W(h,b) = 0
W(h,c) = 1
W(a,b) = 0
W(a,c) = 1
W(a,h) = 2
Spring 2016, Feb 17 . . .
Positive cycle;
no solution for
longest path
0
-1
0
rb
-1
rc
0
0
Constraint graph
0
D(h,a) = 10
D(h,b) = 15
D(h,c) = 20
D(a,b) = 15
D(a,c) = 20
D(a,h) = 20
W(b,c) = 1
W(b,h) = 2
W(b,a) = 2
W(c,h) = 1
W(c,a) = 1
W(c,b) = 1
ELEC 7770: Advanced VLSI Design (Agrawal)
D(b,c) = 10
D(b,h) = 10
D(b,a) = 20
D(c,h) = 5
D(c,a) = 15
D(c,b) = 20
34
Timing Optimization, T = 11.25?
15
-1
11.25
1
1
rh
0
0
ra
-1
rh = 0
rb = 1
rc = 0
ra = 0
0
0
rb
-1
rc
-1
0
0
Constraint graph
0
W(h,a) = 0
W(h,b) = 0
W(h,c) = 1
W(a,b) = 0
W(a,c) = 1
W(a,h) = 2
Spring 2016, Feb 17 . . .
D(h,a) = 10
D(h,b) = 15
D(h,c) = 20
D(a,b) = 15
D(a,c) = 20
D(a,h) = 20
W(b,c) = 1
W(b,h) = 2
W(b,a) = 2
W(c,h) = 1
W(c,a) = 1
W(c,b) = 1
ELEC 7770: Advanced VLSI Design (Agrawal)
D(b,c) = 10
D(b,h) = 10
D(b,a) = 20
D(c,h) = 5
D(c,a) = 15
D(c,b) = 20
35
Retiming Graph
a
10
b
5
FF
5
c
1
h
0
rh = 0
0
a
10
ra = 0
0
1
b
5
1
0
rb = 1
c
5
rc = 0
wij_retimed = wij + rj – ri
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Retimed Circuit
a
10
FF
b
5
Logic optimization
will remove these.
1
h
0
rh = 0
0
a
10
ra = 0
1
5
c
b
5
0
rb = 1
c
5
rc = 0
Critical Path = 10
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Correlator Circuit
f
g
0
7
0
h
rh=0
7
rf=0
rg=0
1
3
ra=0 a
0
0
0
0
Critical path delay = 24
e
0
7 re=0
0
3
1
b
3
rb=0
1
c rc=0
1
3
rd=0
d
Initial retiming vector = {0,0,0,0,0,0,0,0}
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Retiming Optimization
24
18
15
13.5
12
Critical path delay
Retiming vector
{ra,rb,rc,rd,re,rf,rg,rh}
24
{0,0,0,0,0,0,0,0}
12
Not feasible
18
15
0
Spring 2016, Feb 17 . . .
{-1,-1,-2,-2,-2,-1,0,0}
{-1,-1,-2,-2,-2,-1,0,0}
13.5
{-1,-1,-2,-2,-2,-1,0,0}
12.75
Not feasible
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Retiming of Correlator Circuit
0→1
7
0
h
rh=0
rg=0
0→1
0
1→0
Critical path delay = 13.5
e
0→2→1
7
7 re= -2
rf= -1
0→2→0
0→1→0 0→2→0
f
g
3
ra= -1 a
1→2→1
3
b
1→2→0
rb= -1
3
1→3→1
c rc= -2
3
rd= -2
d
retiming vector = {-1,-1,-2,-2,-2,-1,0,0}
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Retimed Correlator Circuit
1
7
0
h
rh=0
rg=0
0→1
0
0
Critical path delay = 13
e
1
7
7 re= -2
rf= -1
0
0
0
f
g
3
ra= -1 a
3
1
b
0
rb= -1
3
1
c rc= -2
3
rd= -2
d
retiming vector = {-1,-1,-2,-2,-2,-1,0,0}
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References
 C. E. Leiserson, F. Rose and J. B. Saxe, “Optimizing



Synchronous Circuits by Retiming,” Proc. 3rd Caltech
Conf. on VLSI, 1983, pp. 87-116.
C. E. Leiserson and J. B. Saxe, “Retiming Synchronous
Circuitry,” Algorithmica, vol. 6, pp. 5-35, 1991.
G. De Micheli, Synthesis and Optimization of Digital
Circuits, New York: McGraw-Hill, 1994, Section 9.3.1.
N. Maheshwari and S. S. Sapatnekar, Timing Analysis
and Optimization of Sequential Circuits, Boston:
Springer, 1999, Chapter 4.
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