Transcript Lecture 5: Timing Verification and Optimization

ELEC 7770
Advanced VLSI Design
Spring 2016
Timing Verification and Optimization
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University, Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr16/course.html
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Proof of Correctness
 Static timing analysis proves the timing



correctness. That is, the circuit is guaranteed to
work at the clock rate determined by the critical
path.
But the circuit may also work correctly at faster
speeds.
Because the critical path identified by STA
(static timing analysis) may be a “false path”.
STA overestimates the delay of the circuit.
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Static Path Sensitization
 Definition: Propagation of a signal value through

a path to a primary output.
Example:
0
1
Sensitized path
Stuck-at faults here
are testable
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Statically Unsensitized Path
 Definition: Signal cannot be propagated through


a unsensitized path.
Cause: Off-path inputs cannot be set to required
values.
Example:
Off-path inputs
0 or 1
Stuck-at faults here
are not testable
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Unensitized path
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Dynamically Sensitized Path
 Definition: A dynamic signal can be propagated

through a statically unsensitizable path.
Example: See later.
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False and True Paths
 A false path cannot propagate an event and hence

cannot affect the timing of the circuit. False paths are
dynamically unsensitizable.
Dynamically sensitizable path (true path): All off-path
inputs must settle down to their non-controlling values
when the event propagates through the path.
a
b
c
1
0
d 1
True path of length 3
e
y
2
1
f
1
1
3
z
1
0
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True path of
length 4
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Static Sensitization of Path
 Static sensitization of path: All off-path inputs can be

simultaneously set to their non-controlling values.
Longest path in the following example is statically
unsensitizable. Such paths are often referred to, though
not correctly (why?), as false paths.
True path of length 3
a
d 1
1
e
2
1
1
b
0
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y
1
3
1
1
z
f
1
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False path of
length 4
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An Example
 Statically unsensitizable (false) path.
 P. C. McGeer and R. K. Brayton, Integrating
Functional and Temporal Domains in Logic
Design, Springer, 1991.
a
False path of delay 3
e
1
0
0
1
g
d
b
c
1
1
1
f
0
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Example (Cont.)
 Another statically unsensitizable false path.
 P. C. McGeer and R. K. Brayton, Integrating
Functional and Temporal Domains in Logic
Design, Springer, 1991.
a
1
Two false paths of delay 3
e
1
0
0
1
g
d
b
c
1
1
f
0
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Example (Cont.)
 Two paths are dynamically sensitizable and will affect the

timing if both are together faulty.
P. C. McGeer and R. K. Brayton, Integrating Functional
and Temporal Domains in Logic Design, Springer, 1991.
a
False paths of delay 3
e
1
2 3
1
g
d
b
c
1
1
f
0
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Static Sensitization Condition
x
y
z
Off-path inputs
There must exist an input vector (PI) that satisfies the following conditions:
∂y/∂x = 1, ∂z/∂y = 1, . . .
Where ∂y/∂x = y(x=1, PI)  y(x=0, PI) is Boolean difference
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An ATPG Method
x
y
z
Stuck-at-0
Path is false if this
fault is redundant
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Optimism and Pessimism
Statically
Dynamically
sensitizable
sensitizable
Paths
paths
(optimistic)
Structural paths analyzed by STA (pessimistic)
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Theorem 1
 Every statically sensitizable path is dynamically


sensitizable.
Proof: Since a vector exists to sensitize the path,
if that vector does not specify the path input,
then toggling the primary input at the origin of
the path will propagate an event through the
path.
P. C. McGeer and R. K. Brayton, Integrating
Functional and Temporal Domains in Logic
Design, Springer, 1991, p. 35.
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Theorem 2
 The longest path in a circuit is dynamically


sensitizable iff it is statically sensitizable.
Proof: Because this is the longest path, all offpath inputs will settle to their sensitizing values
at the inputs of any gate before the on-path
event propagates through that gate.
P. C. McGeer and R. K. Brayton, Integrating
Functional and Temporal Domains in Logic
Design, Springer, 1991, p. 37.
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Proof of Theorem 2
 Case 1: Static sensitization does not specify the


value at the path origin.
Toggling the path origin will propagate an event
through the path causing dynamic sensitization.
Example:
1
0
A 01 or 10
here will propagate
through the path
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Statically sensitized longest path
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Proof of Theorem 2 (Cont.)
 Case 2: Static sensitization specifies the value at the path origin.
 Toggling the path origin will propagate an event through the path
causing dynamic sensitization because the event on the longest
path will see all gates sensitized through shorter paths.
 Example:
This event
Shorter path sets this to
1 before the event arrives on
the longest path
0
propagated
through
longest path
01
0
01
Apply 10 event here
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Statically sensitized longest path
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Proof of Theorem 2 (Cont.)
 Case 3: Longest path is statically unsensitizable.
 Toggling the path origin will not propagate any

event through the path. Toggling other input only
dynamically sensitizes shorter path.
This event did
Example:
Shorter paths set these to
01 before the event arrives on
the longest path
01
01
not propagate
through
longest path
01
10
01
Statically unsensitizable longest path
Apply events
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Speeding Up a Circuit
2
False path
w
a
x
2
w
a
3
u
2
2
v
2
y
z
u
v
x
y
z
0 1 2 3 4 5 6 7 time
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Speeding Up a Circuit
2
False path
w
a
x
2
w
a
3
u
2
2
v
2
y
z
u
v
x
y
z
0 1 2 3 4 5 6 7 time
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Speeding Up a Circuit
Reducing the delay of a false path can increase circuit delay.
2
w
a
x
2
w
a
1
u
2
2
v
2
y
z
u
v
x
y
z
0 1 2 3 4 5 6 7 time
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Speeding Up a Circuit
2
False path
w
a
x
2
w
a
1
u
2
2
v
2
y
z
u
v
x
y
z
0 1 2 3 4 5 6 7 time
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A Delay Optimization Algorithm
 REDUCE_DELAY (Circuit graph (V, E), ε)
Repeat {
Compute critical paths and critical delay Δ
Set output data ready time to Δ
Compute slacks
U = vertex subset with slack < ε
W = select vertices in U
Apply transformation to vertices in W
} until (no transformation can reduce Δ)

}
G. De Micheli, Synthesis and Optimization of Digital
Circuits, McGraw-Hill, 1994, p. 427.
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Example: Critical Path Delay
Compute data ready time from input to output
a 0
b
c
0
2
2
1
3
0
2
0
d
e
3
3
2
5
1
8
1
2
11
x
9
6
0
g
2
8
y
0
Critical path delay, Δ = 11
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Example: Gate Slack Calculation (1)
Maximum time from input
a 0
b
c
0
2
2
1
3
0
2
0
d
e
3
3
2
5
1
8
1
2
11
x
9
6
0
g
2
8
y
0
Critical path delay, Δ = 11
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Example: Gate Slack Calculation (2)
2
a 0
b
c
Maximum time to output
08
2
0
8
11
0
3
d
e 0
8
g
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1
3
5
2
8
3
0
2
2
6
2
5
6
1
8
3
6
5
2
8
0
1
2
9
2
11
0
y
0
Critical path delay, Δ = 11
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x
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Example: Gate Slack Calculation (3)
2
a 0
b
c
Delay of longest path through gate
2
08 8
8
08
11 11 8
3
0
3
d
e 0
8
8
g
0
2
2
8 2
6
8
1
3
5
11
2
11
2
5
6
11
1
8
3
6
5
8
2
2
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11
8
0
11
1
2
9
2
11
0
y
0
Critical path delay, Δ = 11
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x
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Example: Gate Slack Calculation (4)
Gate slack = Δ – Delay of longest path through gate
a2 9
b
c
3 8
2
8 3
8
1
3
11
3 8
11
0
d
e
11
3
2
11
0
8 3
g 9
2
0
11
1
0
11
1
2
0
11
0
0
8
2
3
y
2
Critical path delay, Δ = 11
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x
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Speeding Up
9
a
b
c
3
2
3
1
3
3
0
d
e
3
U
0
2
0
1
0
2
0
Split critical path
3
g 9
1
2
2
0
0
3
y
Critical path delay, Δ = 11
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x
29
Split Critical Path
a
b
c
2
V
1
1
2
U=0
2
U=1
d
3
2
1
U
1
0
2
1
V
1
0
x
2
V
1
aV
0 or 1
e
y
2
g
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Synthesize Multiplexer
U
1
U
2
2
U
aV
U
2
x
U
2
aV
U
aV
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x
2
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2
x
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Split Critical Path
a
b
c
2
1
aV
aV
V
1
2
2
X
Δ=8
d
3
2
1
U
e
y
2
g
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Alternative Transformation (1)
a
b
c
2
1
2
d
e
3
2
1
2
x
1
g
y
2
Δ = 11
x = a’ + b’ + c’ + d’ + e’
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Alternative Transformation (2)
a
b
c
2
1
2
d
e
3
2
1
2
x
Isolate and resynthesize
1
g
y
2
Δ = 11
x = a’ + b’ + c’ + d’ + e’,
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all inputs are symmetric.
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Alternative Transformation (3)
d
3
b
c
2
a
e
1
2
1
2
1
2
1
2
x
y
2
g
Δ=8
x = a’ + b’ + c’ + d’ + e’,
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a and d are interchanged.
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32-bit Ripple-Carry Adder
Δ
c0
a0
b0
sum0
FA0
a1
b1
Δ = delay of one full adder
sum1
FA1
a2
b2
sum2
FA2
sum31
32Δ
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a31
b31
FA31
c31
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One-Bit Full-Adder Circuit
ci
ai
bi
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FAi
XOR
AND
sumi
XOR
AND
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OR
Ci+1
37
Speeding Up the Adder
b0-b15
cin
a16-a31
b16-b31
0
a16-a31
b16-b31
1
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16-bit
ripple
carry
adder
16-bit
ripple
carry
adder
16-bit
ripple
carry
adder
sum0-sum15
0
1
Multiplexer
a0-a15
sum16-sum31, c31
This is a carry-select adder
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