Transcript Lecture 2: Yield, Quality and Moore's Law

ELEC 7770
Advanced VLSI Design
Spring 2016
Yield, Quality and Moore’s Law
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University
Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr16/course.html
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VLSI Chip Yield
 A manufacturing defect is a finite chip area with


electrically malfunctioning circuitry caused by
errors in the fabrication process.
A chip with no manufacturing defect is called a
good chip.
Fraction (or percentage) of good chips produced
in a manufacturing process is called the yield.
Yield is denoted by symbol Y.
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Importance of Yield
 Cost of a chip =
Cost of fabricating and testing a wafer

Yield × Number of chip sites on the wafer
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Clustered VLSI Defects
Good chips
Faulty chips
Defects
Wafer
Unclustered defects
Wafer yield = 12/22 = 0.55
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Clustered defects (VLSI)
Wafer yield = 17/22 = 0.77
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Yield Parameters
 Defect density (d ) = Average number of defects per unit



chip area
Chip area (A )
Clustering parameter (a)
Negative binomial distribution of defects,
p (x )
= Prob(number of defects on a chip = x )
Γ (α +x )
(Ad / α) x
=  . 
x ! Γ (α)
(1+Ad / α) α+x
where Γ is the gamma function
α = 0, p (x ) is a delta function (max. clustering)
α =  , p (x ) is Poisson distribution (no clustering)
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Yield Equation
Y = Prob( zero defect on a chip ) = p (0)
Y = ( 1 + Ad / α ) – α
Example: Ad = 1.0, α = 0.5, Y = 0.58
Unclustered defects: α = , Y = e
– Ad
Example: Ad = 1.0, α = , Y = 0.37
too pessimistic !
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Effect of Defect Clustering
1.00
Ad = 0.5
Yield
0.75
e-0.5 = 0.607
0.50
0.25
0.00
0
0.5
1.0
1.5
2.0
Clustering Parameter, α
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0.906
0.5
0.27
Yield of
1 cm2 chip
0.913
0.1
Initial process
5.0
Mature process
Clustering parameter, α
Ranges of Yield Parameters
0.50
1.5
Defect density, d in defects per cm2
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References
 Clustered yield model
 M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for
Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000,
Chapter 3.
 C. H. Stapper, “On Yield, Fault Distributions, and Clustering of
Particles,” IBM Jour. of Res. and Dev., vol. 30, no. 3, pp. 326-338,
May 1986.
 The unclustered defect model was first described in paper:
 B. T. Murphy, “Cost-Size Optima of Monolithic Integrated Circuits,”
Proc. IEEE, vol. 52, no. 12, pp. 1537-1545, December 1964.
 A general reference on clustered distributions:
 A. Rogers, Statistical Analysis of Spatial Dispersions, London, United
Kingdom: Pion Limited, 1974.
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Defect Level or Reject Ratio
 Defect level (DL) is the ratio of faulty chips



among the chips that pass tests.
DL is measured as parts per million (ppm).
DL is a measure of the effectiveness of tests.
DL is a quantitative measure of the
manufactured product quality. For
commercial VLSI chips a DL greater than 500
ppm is considered unacceptable.
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Determination of DL
 From field return data: Chips failing in the

field are returned to the manufacturer.
The number of returned chips normalized
to one million chips shipped is the DL.
From test data: Fault coverage of tests
and chip fallout rate are analyzed. A
modified yield model is fitted to the fallout
data to estimate the DL.
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Percentage of chips passing test
Testing and Defect Level
100
Test yield = 62%
60
True yield = 60%
Defect level = 32,258 PPM
0
0
moderate
Testing
stopped
high
Testing cost
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Test Data Analysis for DL
 Define three parameters:
 Fault density, f = average number of stuck-at
faults per unit chip area
 Fault clustering parameter, b
 Stuck-at fault coverage, T
 New yield parameters:
 d → f, Ad → TAf
α→b
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Fault-Based Yield Equation
 Replace defects with modeled faults:
Y (T ) = (1 + TAf / b)
–b
 Assume that tests with 100% fault coverage
(T = 1.0) will remove all faulty chips,
Y = Y (1) = (1 + Af / b) – b
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Defect Level
Y (T ) – Y (1)
DL (T ) = ———————
Y (T )
b
( b + TAf )
= 1 – ——————
b
( b + Af )
Where T is the fault coverage of tests, Af is the
average number of faults on the chip of area A, β
is the fault clustering parameter. Af and β are
determined by test data analysis.
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Example: SEMATECH Chip
 Bus interface controller ASIC fabricated and







tested at IBM, Burlington, Vermont
116,000 equivalent (2-input NAND) gates
304-pin package, 249 I/O
Clock: 40MHz, some parts 50MHz
0.8m CMOS, 3.3V, 9.4mm x 8.8mm area
Full scan, 99.79% fault coverage
Advantest 3381 ATE, 18,466 chips tested at
2.5MHz test clock
Data obtained courtesy of Phil Nigh (IBM)
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Stuck-at fault coverage, T
Test Coverage from Fault Simulator
Vector number
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Measured chip fallout, 1 – Y (T )
Measured Chip Fallout
Vector number
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Chip fallout and computed 1 – Y (T )
Model Fitting
Chip fallout vs. fault coverage
Y (1) = 0.7623
Measured chip fallout
Y (T ) for Af = 2.1 and b = 0.083
Stuck-at fault coverage, T
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Computed DL
Defect level in ppm
237,700 ppm (Y = 76.23%)
Stuck-at fault coverage (%)
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Summary
 VLSI yield depends on two process parameters,





defect density (d ) and clustering parameter (α).
Yield drops as chip area increases; low yield
means high cost.
Fault coverage measures the test quality.
Defect level (DL) or reject ratio is a measure of
chip quality.
DL can be determined by an analysis of test
data.
For high quality: DL << 500 ppm, fault coverage
~ 99%
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Two Problems to Solve
1. Using the expression for defect level on Slide
15, derive test coverage (T ) as a function of
fault clustering parameter (β), defect level
(DL), and average number of faults (Af ) on a
chip.
2. Find the defect level for:
 Fault density, f = 1.45 faults/sq. cm
 Fault clustering parameter, β = 0.11
 Chip area = 1 cm2
 Fault Coverage, T = 95%
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Solution to Problem 1
Defect level, DL, is given on Slide 15, as follows:
DL = 1 – [(β + TAf )/(β + Af )]β
where T is the fault coverage, Af is the average number of
faults on a chip of area A, and β is a fault clustering
parameter. Further manipulation of this equation leads to the
following result:
(1 – DL)1/β = (β + TAf )/(β + Af )
or
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T = [{(β + Af )(1 – DL)1/β – β}/(Af )] × 100 percent
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Solution to Problem 2
Defect level, DL, as given on Slide 15, is:
DL(T ) = 1 – [(β + TAf )/(β + Af )]β
Substituting,
 Fault density, f = 1.45 faults/sq. cm
 Fault clustering parameter, β = 0.11
 Chip area = 1 cm2
 Fault Coverage, T = 95%
We get,
DL(T ) = 0.00522 or 5,220 parts per million
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Gordon E. Moore
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1965
 “Cramming More Components onto Integrated

Circuits,” Electronics, vol. 38, no. 8, April 19, 1965.
The complexity for minimum component costs has
increased at a rate of roughly a factor of two per year
(see graph on next page). Certainly over the short
term this rate can be expected to continue, if not to
increase. Over the longer term, the rate of increase
is a bit more uncertain, although there is no reason
to believe it will not remain nearly constant for at
least 10 years. That means by 1975, the number of
components per integrated circuit for minimum cost
will be 65,000.
I believe that such a large circuit can be built on
a single wafer.
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Moore’s 1965 Graph
Shrinking features
Increase defect
density
Components per unit area
Increased by reducing
Feature size
1975
Shrinking feature size →
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Economics of VLSI
 Assume wafer size and processing cost are

fixed.
Increasing chip area will:
 Reduce number of chips on a wafer
 Reduce yield
 Increase chip cost
Chip cost
=
Cost of fabricating and testing a wafer

Yield × Number of chip sites on the wafer
 Increase functionality also
 Cost per function should be minimized.
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Increasing Functionality/Area
 Increase number of transistors per unit area:
 Shrink feature size (λ)
 Each generation of VLSI technology reduces λ by a



factor 1/√2 = 0.707, doubling number of transistors
per unit area
Assume defect density d = k/λ, where k is a constant
of proportionality (technology parameter)
Area of a component (transistor) is k’λ, where k’ is a
constant (technology parameter)
On chip of area A, number of transistors t = A/(k’λ)
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Component (Transistor) Cost, Ct
 Ct = Chip cost/Number of transistors
=
Wafer cost (Wc)
k’λ
̶̶̶̶̶̶̶̶̶̶̶̶̶̶̶̶̶̶̶̶̶̶̶̶̶̶̶̶̶̶̶̶̶̶̶̶̶̶ . ̶̶̶̶̶̶
Y × Wafer area (Wa)/A
A
=
Wc k’λ
Wc
̶ ̶ ̶ ̶ ̶ ̶ ̶ ̶ ̶ ̶ ̶ ̶ ̶ ̶ ̶ ̶ ̶ ̶ ̶ ̶ ̶ ̶ ̶ ̶ ̶ ̶ ̶ ̶ ̶ = ̶ ̶ ̶ ̶ ̶ ̶ k’λ (1 + kk’t / a)a
Wa (1 + Ad/ a) – a
Wa
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Cost per transistor
Component Cost
k’λ
(1 + kk’t / a)a
Number of transistors, t →
←λ
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Cost per transistor
Technology Advances
k’λ
(1 + kk’t / a)a
Number of transistors, t →
←λ
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1975
 “Progress in Digital Integrated Electronics,”

IEDM Tech. Digest, 1975, pp. 11-13.
. . . the rate of increase of complexity can be
expected to change slope in the next few years
as shown in Figure 5. The new slope might
approximate a doubling every two years, rather
than every year, by the end of the decade.
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Figure 5 of Moore’s 1975 Paper
Components per chip
16M
1M
64K
4K
256
16
1
60
65
70
75
80
85
Year
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1995
 “Lithography and the Future of Moore’s Law,”

Proc. SPIE, vol. 2437, May 1995.
By making things smaller, everything gets better
simultaneously. There is little need for trade-offs.
The speed of our products goes up, the power
consumption goes down, system reliability, as
we put more of the system on a chip, improves
by leaps and bounds, but especially the cost of
doing thing electronically drops as a result of the
technology.
(SPIE – Society of Photonic Instrumentation Engineers)
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Also in the 1995 Paper
. . . I have no idea what will happen beyond 0.18 microns.
In fact, I still have trouble believing we are going to be
comfortable at 0.18 microns using conventional optical
systems. Beyond this level, I do not see any way that
conventional optics carries us any further. Of course,
some of us said this about the one micron level. This
time, however, I think there are fundamental materials
issues that will force a different direction. The people at
this conference are going to have to come up with
something new to keep us on the long term trend.
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Source: Wikipedia
Moore’s Law
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2016
 Problems arising with technology advances:
 High power consumption
 Power density
 Leakage
 Process variation – larger as a fraction of feature size
 Increased noise sensitivity
 Problems with design:
 Verification of correctness – logic and timing
 Ensuring reliable operation
 Testing complexity – time and cost
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