Lecture 16: Technology Mapping
Download
Report
Transcript Lecture 16: Technology Mapping
ELEC 7770
Advanced VLSI Design
Spring 2014
Technology Mapping
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University
Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14
Spring 14, Apr 25 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
1
Synthesis: A Two-Step Process
Minimization – Obtain MSOP or MPOS. This is
also known as two-level minimization because
the result can be implemented as a two-level
AND-OR or NAND-NAND or NOR-NOR circuit.
Technology mapping – Considering design
requirements, transform the minimized form into
one of the technologically realizable forms:
Spring 14, Apr 25 . . .
Programmable logic array (PLA)
Standard cell library
Field programmable gate array (FPGA)
Other . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
2
Standard-Cell Design
Obtain two-level minimized form.
Map the design onto predesigned building blocks called
standard cells (technology mapping).
Standard-cell library contains predesigned logic cells in
the technology of manufacture. Examples of technology:
90 nanometer CMOS
65 nanometer CMOS
45 nanometer CMOS
...
Optimize for area, delay, power, testability.
Spring 14, Apr 25 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
3
A Technology Mapping Algorithm
Use a small set of logic elements as building
blocks, sufficient to construct any logic circuit.
For example, NAND. Building blocks may be
two-input NAND gate and inverter.
MSOP is converted into NAND-NAND circuit.
Split all NAND gates of the circuit into two-input
NANDs and inverters.
Cover the circuit with standard cells, also split into
two-input NAND gates and inverters (graphmatching).
Spring 14, Apr 25 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
4
A Typical Cell Library
Name
Area units (cost)
Inputs
Inverter
2
A
NAND2
3
A, B
NAND3
4
A, B, C
NAND4
5
A, B, C, D
AOI21
4
A, B, C
OAI21
4
A, B, C
AOI22
5
A, B, C, D
XOR
4
A, B
Output function, Z
ZA
Z AB
Z ABC
Z ABCD
Z AB C
Z ( A B)C
Z AB CD
Z AB AB
S. Devadas, A. Ghosh and K. Keutzer, Logic Synthesis, New York: McGraw-Hill
1994, Section 7.7, pp. 185-198.
Spring 14, Apr 25 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
5
NAND3 Cell
Directed Acyclic
Graph (DAG)
(tree)
Spring 14, Apr 25 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
6
NAND4 Cell
Spring 14, Apr 25 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
7
AOI21 Cell
Spring 14, Apr 25 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
8
OAI21 Cell
Spring 14, Apr 25 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
9
AOI22 Cell
Spring 14, Apr 25 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
10
Technology Mapping Procedure
Obtain minimum sum of products (MSOP).
Convert to two-level AND-OR circuit.
Transform to two-level NAND-NAND circuit.
Transform to two-input NAND and inverter tree
network.
Perform an optimal pattern matching to obtain a
minimum cost tree covering.
Spring 14, Apr 25 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
11
Example: A Two-Output Function
Need four products: P1, P2, P3, P4
A
F1
0
4
12
A
F2
8
0
4
12
8
1
1
5
1
3
C
13
1
7
1
15
1
2
6
9
1
13
1
11
1
14
5
10
9
1
D
3
C
7
15
1
2
6
1
14
1
D
11
1
10
1
B
Spring 14, Apr 25 . . .
B
ELEC 7770: Advanced VLSI Design (Agrawal)
12
Two-Level AND-OR Implementation
Also known as technology-independent circuit.
INPUTS
C
AND
OR
P1
F1
P2
A
P3
B
F2
P4
D
Spring 14, Apr 25 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
13
A NAND Implementation
INPUTS
C
NAND
NAND
P1
F1
P2
A
P3
B
D
Spring 14, Apr 25 . . .
F2
P4
ELEC 7770: Advanced VLSI Design (Agrawal)
14
A Simple Technology Mapping
NAND2 (3)
C
NAND2 (3)
(2)
F1
D
NAND3 (4)
B
P2
(2)
NAND3 (4)
F2
NAND2 (3)
A
Cost = 24
NAND2 (3)
Spring 14, Apr 25 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
15
Improved Design: Represent Circuit
as a Directed Acyclic Graph (DAG)
C
P1
F1
A
P2
P3
B
D
Spring 14, Apr 25 . . .
P4
ELEC 7770: Advanced VLSI Design (Agrawal)
F2
Each node is a
NAND gate.
16
Split DAG into Trees (Forest)
C
D
F1
P2
C
B
D
P2
A
P2
B
A
F2
D
Spring 14, Apr 25 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
17
Use Only Inverter and 2-Input NAND
Spring 14, Apr 25 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
18
Forest with NOT and 2-Input NAND
C
D
F1
P2
B
C
D
P2
P2
A
F2
B
A
D
Spring 14, Apr 25 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
19
Graph Matching from Library
C
OAI21 (4)
D
(2)
Nodes inserted
For pattern matching
F1
P2
B
NAND3 (4)
C
P2
D
P2
NAND2 (3)
A
NAND3 (4)
Cost = 22
F2
B
(2)
A
D
Spring 14, Apr 25 . . .
NAND2 (3)
ELEC 7770: Advanced VLSI Design (Agrawal)
20
Improved Technology Mapping
C
AOI21 (4)
(2)
D
NAND3 (4)
B
F1
P2
(2)
NAND3 (4)
F2
NAND2 (3)
A
Cost = 22
NAND2 (3)
Spring 14, Apr 25 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
21
References
G. De Micheli, Synthesis and Optimization of
Digital Circuits, New York: McGraw-Hill, 1994.
S. Devadas, A. Ghosh and K. Keutzer, Logic
Synthesis, New York: McGraw-Hill, 1994.
K. Keutzer, “DAGON: Technology Binding and
Local Optimization by DAG Matching,” Proc.
24th Design Automation Conf., 1987, pp. 341347.
Spring 14, Apr 25 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
22