Transcript Lecture 11: Zero-Skew Clock Routing

ELEC 7770
Advanced VLSI Design
Spring 2014
Zero-Skew Clock Routing
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University
Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14/course.html
Spring 2014, Mar 17 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
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Zero-Skew Clock Routing
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CK
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Zero-Skew: References
 H-Tree
 A. L. Fisher and H. T. Kung, “Synchronizing Large
Systolic Arrays,” Proc. SPIE, vol. 341, pp. 44-52, May
1982.
 A. Kahng, J. Cong and G. Robins, “High-Performance
Clock Routing Based on Recursive Geometric
Matching,” Proc. Design Automation Conf., June
1991, pp. 322-327.
 M. A. B. Jackson, A. Srinivasan and E. S. Kuh, “Clock
Routing for High-Performance IC’s,” Proc. Design
Automation Conf., June 1990, pp. 573-579.
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Zero-Skew Routing
 Build clock tree bottom up:
 Leaf nodes are all equal loading flip-flops.
 Two zero-skew subtrees are joined to form a larger zero-skew
subtree.
 Entire clock tree is built recursively.
 R.-S. Tsay, “An Exact Zero-Skew Clock Routing

Algorithm,” IEEE Trans. CAD, vol. 12, no. 2, pp. 242249, Feb. 1993.
J. Rubenstein, P. Penfield and M. A. Horowitz, “Signal
Delay in RC Tree Networks,” IEEE Trans. CAD, vol. 2,
no. 3, pp. 202-211, July 1983.
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Balancing Subtrees (1)
xL
r1
c1/2
A
c1/2
t1
C1
Subtree 1
Tapping point
(1 – x)L
r2
c2/2
B
c2/2
t2
C2
Subtree 2
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Balancing Subtrees (2)
 Subtrees 1 and 2 are each balanced (zero


skew) trees, with delays t1 and t2 to respective
leaf nodes.
Total capacitances of subtrees are C1 and C2,
respectively.
Connect points A and B by a minimum-length
wire of length L.
Determine a tapping point x such that wire
lengths xL and (1 – x)L produce zero skew.
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Balancing Subtrees (3)
 Use Elmore delay formula:

0.69 r1(C1 + c1/2) + t1 = 0.69 r2(C2 + c2/2) + t2
Substitute:
 r1 = axL, r2 = a(1 – x)L
 c1 = bxL, c2 = b(1 –x)L
abL2x + aL(C1+C2)x = 1.45 (t2 – t1) + aL(C2+bL/2)
 Then solve for x:
1.45 (t2 – t1) + aL (C2 + bL/2)
x = ───────────────────
aL(bL + C1 + C2)
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Balancing Subtrees Example 1
 Subtree parameters:


 Subtree 1: t1 = 5ps, C1 = 3pF
 Subtree 2: t2 = 10ps, C2 = 6pF
Interconnect:
 L = 1mm
 Wire parameters: a = 100Ω/cm, b = 1pF/cm
Tapping point:
X =
1.45(t2 – t1) + aL (C2 + bL/2)
1.45(10–5) + 100×0.1(6 + 1×0.1/2)
────────────────── = ──────────────────────
aL (bL + C1 + C2)
100×0.1(1×0.1+3+6)
= 1.45(5 + 60.5)/(10×9.1) = 0.7445
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Example 1
FF
t1 = 5ps, C1 = 3pF
0.77445mm
FF
FF
Subtree 1
FF
To next
level
FF
0.2555mm
t2 = 10ps, C2 = 6pF
FF
Subtree 2
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ELEC 7770: Advanced VLSI Design (Agrawal)
FF
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Balancing Subtrees, x > 1
 Tapping point set at root of tree with larger loading (C2, t2).
 Wire to the root of other tree is elongated to provide



additional delay. Wire length L is found as follows:
Set x = 1 in abL2x + aL(C1+C2)x = 1.45(t2 – t1)+aL(C2+bL/2)
i.e., L2 + (2C1/b)L – 2.9 (t2 – t1)/(ab) = 0
Wire length is given by:
[(aC1)2 + 2.9 ab(t2 – t1)]½ – aC1
L
=
────────────────────
ab
R.-S. Tsay, “An Exact Zero-Skew Clock Routing Algorithm,”
IEEE Trans. CAD, vol. 12, no. 2, pp. 242-249, Feb. 1993.
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Balancing Subtrees Example 2
 Subtree parameters:


x
=
 Subtree 1: t1 = 2ps, C1 = 1pF
 Subtree 2: t2 = 15ps, C2 = 10pF
Interconnect:
 L = 1mm
 Wire parameters: a = 100Ω/cm, b = 1pF/cm
Tapping point:
1.45(t2 – t1) + aL (C2 + bL/2) 1.45(15–2) + 100×0.1(10 + 1×0.1/2)
─────────────────── = ──────────────────────
aL (bL + C1 + C2)
100×0.1(1×0.1+1+10)
= (18.85 + 100.5)/(10×11.1) = 1.0752
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Example 2, x = 1.0752
Setting x = 1.0,
L
=
[(aC1)2+2.9ab(t2 – t1)]½ – aC1
────────────────────
ab
=
[(100×1)2 + 290 (15 – 2)]½ – 100×1
───────────────────────
100×1
=
0.1735cm
For a wire of 1.735mm length, place the clock feed at one end.
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Example 2, L = 1.735mm
FF
t1 = 2ps, C1 = 1pF
FF
L = 1.7355mm
FF
Subtree 1
FF
To next
level
FF
t2 = 15ps, C2 = 10pF
FF
Subtree 2
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FF
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Balancing Subtrees, x < 0
 Tapping point set at root of tree with smaller loading (C1, t1).
 Wire to the root of other tree is elongated to provide



additional delay. Wire length L found as follows:
Set x = 0 in abL2x + aL(C1+C2)x = 1.45(t2 – t1)+aL(C2+bL/2)
i.e., L2 + (2C2/b)L – 2.9 (t1 – t2)/(ab) = 0
Wire length is given by:
[(aC2)2 + 2.9 ab(t1 – t2)]½ – aC2
L
=
────────────────────
ab
R.-S. Tsay, “An Exact Zero-Skew Clock Routing Algorithm,”
IEEE Trans. CAD, vol. 12, no. 2, pp. 242-249, Feb. 1993.
Spring 2014, Mar 17 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
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Balancing Subtrees Example 3
 Subtree parameters:


x
=
 Subtree 1: t1 = 15ps, C1 = 10pF
 Subtree 2: t2 = 2ps, C2 = 1pF
Interconnect:
 L = 1mm
 Wire parameters: a = 100Ω/cm, b = 1pF/cm
Tapping point:
1.45(t2 – t1) + aL (C2 + bL/2)
1.45(2–15) + 100×0.1(1 + 1×0.1/2)
─────────────────── = ──────────────────────
aL (bL + C1 + C2)
100×0.1(1×0.1+1+10)
= ( – 18.85 + 10.5)/(10×11.1) = – 0.0752
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Example 3, x = – 0.0752
Setting x = 0.0,
L
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=
[(aC2)2+2.9ab(t1 – t2)]½ – aC2
──────────────────
ab
=
[(100×1)2+290 (15 – 2)]½ – 100×1
───────────────────────
100×1
=
0.1735cm
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Example 3, L = 1.255mm
FF
FF
To next
level
t1 = 15ps, C1 = 10pF
FF
L = 1.735mm
FF
Subtree 1
FF
t2 = 2ps, C2 = 1pF
FF
Subtree 2
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FF
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Zero-Skew Design
Delay
=75ns
Delay
= 50ns
Comb.
Comb.
FF A
FF B
FF C
CK
CK
Tck = 75ns
time
Single-cycle path delay
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Nonzero-Skew Design
Delay
=75ns
Delay
= 50ns
Comb.
Comb.
FF A
FF B
FF C
CK
Delay = 25ns
CK
Tck = 50ns
time
Single-cycle path delay
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Optimized Skew Design
Comb. Delay
=75ns
Delay
=75ns
Delay
= 50ns
Comb.
Comb.
FF A
Delay
FF B
SA
CK
Period = T
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SC
SB
Linear program:
FF C
Objective: Minimize T
Constraints (subject to):
SB – SA + T ≥ 75
SC – SB + T ≥ 50
SA – SC + T ≥ 75
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Online LP Solvers
 PHPSimplex solver
 http://www.phpsimplex.com/simplex/simplex.htm?l=en
 LINDO http://www.lindo.com/ (Download)
 File Lec12.ltx
! Lecture 11 example
MIN T
SUBJECT TO
1)
SB - SA + T ≥ 75
2)
SC - SB + T ≥ 50
3)
SA - SC + T ≥ 75
END
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Optimized Skew Design
Comb. Delay
=75ns
Delay
=75ns
Delay
= 50ns
Comb.
Comb.
FF A
Delay
8.33ns
CK
T = 66.67ns
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FF B
16.67ns
ELEC 7770: Advanced VLSI Design (Agrawal)
FF C
0ns
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Conclusion
 Zero-skew design is possible at the layout level.
 Zero-skew usually results in higher clock speed.
 Nonzero clock skews can improve the design
with reduced hardware and/or higher speed.
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