Transcript Lecture 10: A Linear Programming Solution to Clock Constraint Problem

ELEC 7770
Advanced VLSI Design
Spring 2014
A Linear Programming Solution to Clock
Constraint Problem
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University, Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14/course.html
Spring 2014, Mar 5 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
1
A General Sequential Circuit
Inputs
Outputs
Combinational
Logic
Registers
Clock
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ELEC 7770: Advanced VLSI Design (Agrawal)
2
A Level-Sensitive Latch
D
QN
Q
CK
Clock period, Tck
CK
Latch open
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Latch closed
ELEC 7770: Advanced VLSI Design (Agrawal)
Latch open
time
3
Alternative Implementation
Q
D
CK
J. Segura and C. F. Hawkins, CMOS Electronics, How It Works,
How It Fails, Wiley Interscience, 2004, p.137.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Data Must be Stable Before Latch Closes
0→1→0→0→
D=0→1→1
0
1
1→0→1→0→1→
QN
delays
CK = 1 → 1 → 0
1
1
Q
0→0→1→0→1→
0
1→1→0→0→
Unstable state
Clock period, Tck
CK
Latch open
Latch closed
time
Stable data
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Data and Clock Parameters
Clock period, Tck
CK
Latch open
Latch closed
time
Stable data
D
time
Setup time
Q
Hold time
Stable Q
time
CK-to-Q delay
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ELEC 7770: Advanced VLSI Design (Agrawal)
6
Design With Level-Sensitive Latches
PO
Comb.
Logic
Level-sens. Latches
Comb.
Logic
PI
Level-sens. Latches
PI
PO
CK
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ELEC 7770: Advanced VLSI Design (Agrawal)
7
Edge-Triggered Flip-flop
Master latch
D
Slave latch
Q
QN
CK
Hold time
CK
Clock period, Tck
Master open
Setup time
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Slave open
CK-to-Q delay
time
Trigger edges
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A Dynamic Implementation
VDD
CK
CK
D
Q
CK
CK
GND
J. P. Uyemura, Chip Design for Submicron VLSI: CMOS Layout and
Simulation, Thomsom, 2006, p. 229.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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A Static Implementation
VDD
Q
CK
CK
CK
CK
D
GND
J. P. Uyemura, Chip Design for Submicron VLSI: CMOS Layout and
Simulation, Thomsom, 2006, p. 230.
Spring 2014, Mar 5 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
10
Design With Edge-Triggered Flip-Flops
Inputs
Outputs
Combinational
Logic
Flip-flops
Clock
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ELEC 7770: Advanced VLSI Design (Agrawal)
11
Setup Time Constraint
Skew si
FF i
Note: All times for a
FF should be adjusted
by its clock skew.
Skew sj
Combinational path delay
δ(i,j) ≤ d(i,j) ≤ Δ(i,j)
Travel
time
Tsi
Thi
FF j
Arrive no
later than
this
Tsj
time
Tc.Qi
Tck
Clock edge
Constraint:
i.e.,
si + Tc.Qi + Δ(i,j)
Δ(i,j)
≤
≤
sj + Tck – Tsj
Tck – Tsj – Tc-Qi + sj – si
This is known as long path constraint – prevents zero clocking
Spring 2014, Mar 5 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
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Hold Time Constraint
Skew si FF i
Note: All times for a
FF should be adjusted
by its clock skew.
Combinational path delay
δ(i,j) ≤ d(i,j) ≤ Δ(i,j)
FF j
Skew sj
sj – si + Thj
Tsi
Thi
Tsj
time
Tc.Qi
Tck
Clock edge (si)
Constraint:
i.e.,
si + Tc.Qi + δ(i,j) ≥
δ(i,j)
≥
sj + Thj
Thj – Tc.Qi + sj – si
This is known as short path constraint – avoids double clocking
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Solving Hold Time Problem (1)
PO
(FFj)
PI
(FFi)
PO
PI
PO
(FFi)
PI
(FFj)
Fanout node
External edges (variable delays)
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Internal edges (fixed delays)
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Solving Hold Time Problem (2)
 Variables:
 Shortest arrival time at node i = ai
 Longest arrival time at node i = Ai
 Buffer delay on external edge (i,j) = wij
 Constants:
 At PI i: Ai = Λi and ai = λi, user specified.
 At PI (FF) i: Ai = ai = Tc.Qi
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Solving Hold Time Problem (3)
 Constraints:
 At PO i: Ai ≤ Ri and ai ≥ ri, user defined.
 At PO (FF) i:
 ai ≥ Thi, short path constraint.
 Ai ≤ Tck – Tsi, long path constraint.
 Optimization function (a linear approximation to
minimum number of delay buffers):
minimize
∑
wij
all external
edges (i,j)
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Linear Programming Solution (1)
∑
all external
edges (i,j)
minimize
Subject to:
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wij
Aj ≥ Ai + wij
aj ≤ ai + wij
for all i ε Fanin(j)
for all i ε Fanin(j)
Ai ≤ Ri
ai ≥ ri
for all i ε PO
for all i ε PO
Ai ≤ Tck – Tsi
ai ≥ Thi
for all i ε PO(FF i)
for all i ε PO(FF i)
Ai = Λi
ai = λi
for all i ε PI
for all i ε PI
Ai = Tqi
ai = Tqi
for all i ε PI(FF i)
for all i ε PI(FF i)
ELEC 7770: Advanced VLSI Design (Agrawal)
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Linear Programming Solution (2)
 Solution inserts smallest delays in interconnects

to satisfy short path constraints.
Maintains the specified clock period and
satisfies setup time constraints.
Reference:
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N. Maheshwari and S. S. Sapatnekar, Timing Analysis
and Optimization of Sequential Circuits, Springer, 1999.
ELEC 7770: Advanced VLSI Design (Agrawal)
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Shift Register Example 1 (Long Path)
Δ
F1
CK
F2
s1
0
s3
Δ ≤ Delay
su ho
Ck-2-Q
F3
s2
Δ ≤ Delay
su ho
Δ
Zero skew
su ho
Ck-2-Q
Ck-2-Q
2T
T
Δ ≤ Delay
Δ ≤ Delay
su ho
0 s1
Ck-2-Q
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t
su ho
T
s2
Ck-2-Q
su ho
2T
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s3
t
Ck-2-Q
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Shift Register Example 1 (Short Path)
F1
CK
δ
s1
F2
δ
F3
s2
s3
Zero skew F1
su ho
su ho
Ck-2-Q
0
δ≥ Delay
su ho
Ck-2-Q
0
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su ho
Ck-2-Q
t
Ck-2-Q
T
2T
su ho
su ho
Ck-2-Q
T
ELEC 7770: Advanced VLSI Design (Agrawal)
t
Ck-2-Q
2T
Zero skew F2
20
Shift Register Example 1 (Short Path)
δ
F1
CK
F1
s2
T
δ≥ Delay
su ho
s2
F3
s3
su ho
Ck-2-Q
F2
0
F2
s1
su ho
0 s1
δ
T
Ck-2-Q
su ho
Ck-2-Q
su ho
2T
2T
Ck-2-Q
t
Ck-2-Q
su ho
t
Ck-2-Q
nonzero skew F2
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ELEC 7770: Advanced VLSI Design (Agrawal)
21
Shift Register Example 2 (Short Path)
δ
F1
F2
s1
F1
s1
F3
s2
su ho
0
δ
s3
su ho
T
Ck-2-Q
CK
2T
su ho
Ck-2-Q
t
Ck-2-Q
δ ≥ Delay
F2
su ho
0 s2
Ck-2-Q
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su ho
T
Ck-2-Q
ELEC 7770: Advanced VLSI Design (Agrawal)
su ho
2T
t
Ck-2-Q
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Shift Register Example 2 (Long Path)
Δ
F1
s1
F2
F3
s2
Δ ≤ Delay
su ho
Ck-2-Q
Zero skew
su ho
Ck-2-Q
0
s1
2T
Δ ≤ Delay
su ho
Ck-2-Q
T
t
Ck-2-Q
T
su ho
CK
s3
Δ ≤ Delay
su ho
0
Δ
s2
Δ ≤ Delay
su ho
Ck-2-Q
2T s3
t
Ck-2-Q
23
Spring 2014, Mar 5 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)