Transcript Lecture 8: Clock Skew Problem

ELEC 7770
Advanced VLSI Design
Spring 2014
Clock Skew Problem
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University
Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14/course.html
Spring 2014, Feb 21 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
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Single Clock
Data_in
Data_out
Comb.
FF A
FF B
CKA
CKB
CK
CKA
CKB
Single-cycle path delay
Spring 2014, Feb 21 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
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Multiple Clocks
Data_in
Data_out
Comb.
FF A
CKA
FF B
CKB
CKA
CKB
Multi-cycle path delay
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Clock Skew
 Skew is the time delay of clock signal at a flip

flop with respect to some time reference.
For a given layout each flip-flop has a skew,
measured with respect to a common reference.
Skews of flip-flops separated by combinational
paths affect the short-path and long-path
constraints.
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Skews for Single-Cycle Paths
FFi
CKi
Combinational
Block
Delay:
δ(i,j) ≤ d(i,j) ≤ Δ(i,j)
si
FFj
CKj
sj
si and sj are arrival times of clock edges w.r.t. a reference time
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Delay Latch or D-Latch
SR-latch
D
Q
CK
Q
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Setup and Hold Times of Latch
 Signals are synchronized with respect to clock (CK).
 Operation is level-sensitive:
 CK = 1 allows data (D) to pass through
 CK = 0 holds the value of Q, ignores data (D)
 Setup time is the interval before the clock transition
during which data (D) should be stable (not change).
This will avoid any possible race condition.
 Hold time is the interval after the clock transition during
which data should not change. This will avoid data from
latching incorrectly.
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Why Do We Need Setup?
SR-latch
D
Q
CK=1
Latch
open
Q
Legal inputs are
10 or 01 when
Latch closes
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Latch Inputs
tp
1
D
0
time
Ts
Th
Tc.Q
1
CK
0
Tr
time
Tc.Q : Clock to Q delay
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Master-Slave D-Flip-Flop
Master latch
D
Slave latch
Q
Q
CK
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Master-Slave D-Flip-Flop
 Uses two level-sensitive clocked D-latches.
 Transfers data (D) with one clock period delay.
 Operation is edge-triggered:
 Negative edge-triggered, CK = 1→0, Q = D (previous
slide)
 Positive edge-triggered, CK = 0→1, Q = D
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Negative-Edge Triggered D-Flip-Flop
Clock period, Tck
Master open
Slave closed
CK
Slave open
Master
closed
Triggering clock edge
Setup time, Ts
Hold time, Th
Clock-to-Q delay, Tc.Q
D
Data can change
Data
stable
Data can change
Time
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Skews for Single-Cycle Paths
FFi
CKi
Combinational
Block
Delay:
δ(i,j) ≤ d(i,j) ≤ Δ(i,j)
si
FFj
CKj
sj
skews, si and sj are delays from a common clock generator
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Short-Path Constraint (Double-Clocking)
Tck
CKi
si
Not intended
CKj
intended
Thj
sj
δ(i,j)
Condition to avoid double clocking: si + Tc.Q + δ(i,j) ≥ sj + Thj
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Long-Path Constraint (Zero-Clocking)
Tck
CKi
si
intended
Not intended
CKj
sj
Tsj
Tc.Q+
Δ(i,j)
Condition to avoid zero clocking: si + Tc.Q + Δ(i,j) ≤ sj + Tck – Tsj
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Maximum Clock Frequency
Linear program:
Objective function,
Minimize Tck
Subject to constraints, for all flip-flop pairs (i,j),
(1)
si + Tc.Q + δ(i,j) ≥ sj + Thj
short path
(2)
si + Tc.Q + Δ(i,j) ≤ sj + Tck – Tsj
long path
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Effects of Constraints
 Short path:
 Independent of clock
 Minimum path delay: δ(i,j) ≥ sj – si – Tc.Q + Thj
 Long path:
 Minimum clock priod: Tck ≥ si – sj + Tc.Q + Δ(i,j) + Tsj
 Example: Shift register, assume δ(i,j) ≈ Δ(i,j) ≈ 0
 si – sj ≥ Thj – Tc.Q > 0, si > sj for correct operation
 Tck ≥ si – sj + Tc.Q + Tsj, sj > si for maximum speed
 Clock routed opposite to data
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Shift Register Example
Delay ≈ 0
Delay = si
FFi
sj
Delay ≈ 0
FFj
sk
FFk
CK
Ci
Ri
Cj
Rj
si + Tc.Q – sj ≥ Thj
Tck ≥ si – sj + Tc.Q + Tsj
Tck + si + Tc.Q – sj ≥ si – sj + Tc.Q + Tsj + Thj
Maximum clock speed:
Tck = Tsj + Thj
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Ck
Rk
for correct operation
for correct operation
adding two inequalities
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Finding Clock Skews
sk
si
FFi
FFj
FFk
CK
Ri
Ci
Rj
Cj
Rk
Ck
sj
Use Elmore delay formula to calculate si, sj, sk.
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Interconnect Delay: Elmore Delay Model
 W. Elmore, “The Transient Response of Damped Linear
Networks with Particular Regard to Wideband Amplifiers,” J.
Appl. Phys., vol. 19, no.1, pp. 55-63, Jan. 1948.
Ri
i
Rj
CK
Shared resistance:
Rii = Ri
Rij = Rji = Ri
Rik = Rki = Ri
Rjj = Ri + Rj
Rjk = Rkj = Ri + Rj
Rkk = Ri + Rj + Rk
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Ci
Rk
j
Cj
ELEC 7770: Advanced VLSI Design (Agrawal)
k
Ck
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Elmore Delay Calculation
Delay at nodes,
sk
= 0.69 (Ci × Rik + Cj × Rjk + Ck × Rkk )
= 0.69 [Ri Ci + (Ri + Rj) Cj + (Ri + Rj + Rk)Ck]
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sj
= 0.69 [Ri Ci + (Ri + Rj) (Cj + Ck)]
si
= 0.69 [Ri (Ci + Cj + Ck)]
ELEC 7770: Advanced VLSI Design (Agrawal)
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Example
1Ω
i
1Ω
CK
1pF
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1Ω
j
1pF
si
=
0.69 × 3 ps
sj
=
0.69 × 5 ps
sk
=
0.69 × 6 ps
ELEC 7770: Advanced VLSI Design (Agrawal)
k
1pF
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Finding δ(I,j) and Δ(I,j)
Minimum delay
Maximum delay
, -
, -
A
1
, -
, -
0, 0
B
3
3, 3
i
, -
, -
, -
, -
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C
1
D
2
H 9, 10 j
3
E
1
4, 4
G
2
, -
, -
F
1 5, 5
ELEC 7770: Advanced VLSI Design (Agrawal)
6, 7
J 6, 8
1
k
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Maximum Clock Frequency for
Tolerance ±q/2 in Skew
Linear program:
Minimize Tck
Subject to:
For all flip-flop pairs (i,j),
si + δ(i,j) ≥ sj + Thj + q
si + Δ(i,j) ≤ sj + Tck – Tsj – q
Where
q is a constant
si are variables, simin ≤ si
Tck is a variable
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Maximum Tolerance for Given Clock
Frequency
Linear program:
Maximize q
Subject to:
For all flip-flop pairs (i,j),
si + Tc.Qi + δ(i,j) ≥ sj + Thj + q
si + Tc.Qi+ Δ(i,j) ≤ sj + Tck – Tsj – q
Where
Tck, Tc.Qi, Thj and Tsj are constants
si are variables, simin ≤ si
q is a variable
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No solution because of
zero slack.
Increasing skew tolerance q
Tradeoffs
Increasing clock period Tck
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Clock Skew Problem
 N. Maheshwari and S. S. Sapatnekar, Timing

Analysis and Optimization of Sequential Circuits,
Springer, 1999.
J. P. Fishburn, “Clock Skew Optimization,” IEEE
Trans. Computers, vol. 39, no. 7, pp. 945-951,
July 1990.
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