Transcript Lecture 8: Clock Skew Problem

ELEC 7770
Advanced VLSI Design
Spring 2012
Clock Skew Problem
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University
Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr12/course.html
Spring 2012, Feb 22 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
1
Single Clock
Data_in
Data_out
Comb.
FF A
FF B
CKA
CKB
CK
CKA
CKB
Single-cycle path delay
Spring 2012, Feb 22 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
2
Multiple Clocks
Data_in
Data_out
Comb.
FF A
CKA
FF B
CKB
CKA
CKB
Multi-cycle path delay
Spring 2012, Feb 22 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
3
Clock Skew
 Skew is the time delay of clock signal at a flip

flop with respect to some time reference.
For a given layout each flip-flop has a skew,
measured with respect to a common reference.
Skews of flip-flops separated by combinational
paths affect the short-path and long-path
constraints.
Spring 2012, Feb 22 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
4
Skews for Single-Cycle Paths
FFi
CKi
Combinational
Block
Delay:
δ(i,j) ≤ d(i,j) ≤ Δ(i,j)
xi
FFj
CKj
xj
xi and xj are arrival times of clock edges
Spring 2012, Feb 22 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
5
Delay Latch or D-Latch
SR-latch
D
Q
CK
Q
Spring 2012, Feb 22 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
6
Setup and Hold Times of Latch
 Signals are synchronized with respect to clock (CK).
 Operation is level-sensitive:
 CK = 1 allows data (D) to pass through
 CK = 0 holds the value of Q, ignores data (D)
 Setup time is the interval before the clock transition
during which data (D) should be stable (not change).
This will avoid any possible race condition.
 Hold time is the interval after the clock transition during
which data should not change. This will avoid data from
latching incorrectly.
Spring 2012, Feb 22 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
7
Latch Inputs
tp
1
D
0
time
Ts
Th
1
CK
0
Spring 2012, Feb 22 . . .
Tr
ELEC 7770: Advanced VLSI Design (Agrawal)
time
8
Master-Slave D-Flip-Flop
Master latch
D
Slave latch
Q
Q
CK
Spring 2012, Feb 22 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
9
Master-Slave D-Flip-Flop
 Uses two level-sensitive clocked D-latches.
 Transfers data (D) with one clock period delay.
 Operation is edge-triggered:
 Negative edge-triggered, CK = 1→0, Q = D (previous
slide)
 Positive edge-triggered, CK = 0→1, Q = D
Spring 2012, Feb 22 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
10
Negative-Edge Triggered D-Flip-Flop
Clock period, Tck
Master open
Slave closed
CK
Slave open
Master
closed
Triggering clock edge
Setup time
Ts
D
Data can change
Hold time
Th
Data
stable
Data can change
Time
Spring 2012, Feb 22 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
11
Skews for Single-Cycle Paths
FFi
CKi
Combinational
Block
Delay:
δ(i,j) ≤ d(i,j) ≤ Δ(i,j)
xi
FFj
CKj
xj
xi and xj are arrival times of clock edges
Spring 2012, Feb 22 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
12
Short-Path Constraint (Double-Clocking)
Tck
CKi
si
Not intended
CKj
intended
Thj
sj
δ(i,j)
si + δ(i,j) ≥ sj + Thj
Spring 2012, Feb 22 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
13
Long-Path Constraint (Zero-Clocking)
Tck
CKi
si
intended
Not intended
CKj
sj
Tsj
Δ(i,j)
si + Δ(i,j) ≤ sj + Tck – Tsj
Spring 2012, Feb 22 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
14
Maximum Clock Frequency
Linear program:
Objective function,
Minimize Tck
Subject to constraints, for all flip-flop pairs (i,j),
Spring 2012, Feb 22 . . .
(1)
si + δ(i,j) ≥ sj + Thj
short path
(2)
si + Δ(i,j) ≤ sj + Tck – Tsj
long path
ELEC 7770: Advanced VLSI Design (Agrawal)
15
Effects of Constraints
 Short path:
 Independent of clock
 δ(i,j) ≥ sj – si + Thj
 Long path:
 Tck ≥ si – sj + Δ(i,j) + Tsj
 Example: Shift register, δ(i,j) ≈ Δ(i,j) ≈ 0
 si – sj ≥ Thj > 0
si > sj for correct operation
 Tck ≥ si – sj + Tsj
sj > si for maximum speed
 Clock routed opposite to data
Spring 2012, Feb 22 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
16
Shift Register Example
Delay ≈ 0
FFi
Delay = si
sj
Delay ≈ 0
FFj
sk
FFk
CK
Ci
Ri
Cj
Rj
Ck
Rk
si – sj ≥ Thj
for correct operation
Tck ≥ si – sj + Tsj
for correct operation
Maximum clock speed, Tck = Thj + Tsj
Spring 2012, Feb 22 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
17
Finding Clock Skews
sk
si
FFi
FFj
FFk
CK
Ri
Ci
Rj
Cj
Rk
Ck
sj
Use Elmore delay formula to calculate si, sj, sk.
Spring 2012, Feb 22 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
18
Interconnect Delay: Elmore Delay Model
 W. Elmore, “The Transient Response of Damped Linear
Networks with Particular Regard to Wideband Amplifiers,” J.
Appl. Phys., vol. 19, no.1, pp. 55-63, Jan. 1948.
Ri
i
Rj
CK
Shared resistance:
Rii = Ri
Rij = Rji = Ri
Rik = Rki = Ri
Rjj = Ri + Rj
Rjk = Rkj = Ri + Rj
Rkk = Ri + Rj + Rk
Spring 2012, Feb 22 . . .
Ci
Rk
j
Cj
ELEC 7770: Advanced VLSI Design (Agrawal)
k
Ck
19
Elmore Delay Calculation
Delay at nodes,
sk
= 0.69 (Ci × Rik + Cj × Rjk + Ck × Rkk )
= 0.69 [Ri Ci + (Ri + Rj) Cj + (Ri + Rj + Rk)Ck]
Spring 2012, Feb 22 . . .
sj
= 0.69 [Ri Ci + (Ri + Rj) (Cj + Ck)]
si
= 0.69 [Ri (Ci + Cj + Ck)]
ELEC 7770: Advanced VLSI Design (Agrawal)
20
Example
1Ω
i
1Ω
CK
1pF
Spring 2012, Feb 22 . . .
1Ω
j
1pF
si
=
0.69 × 3 ps
sj
=
0.69 × 5 ps
sk
=
0.69 × 6 ps
ELEC 7770: Advanced VLSI Design (Agrawal)
k
1pF
21
Finding δ(I,j) and Δ(I,j)
Minimum delay
Maximum delay
, -
, -
A
1
, -
, -
0, 0
B
3
3, 3
i
, -
, -
, -
, -
Spring 2012, Feb 22 . . .
C
1
D
2
H 9, 10 j
3
E
1
4, 4
G
2
, -
, -
F
1 5, 5
ELEC 7770: Advanced VLSI Design (Agrawal)
6, 7
J 6, 8
1
k
22
Maximum Clock Frequency for
Tolerance ±q/2 in Skew
Linear program:
Minimize Tck
Subject to:
For all flip-flop pairs (i,j),
si + δ(i,j) ≥ sj + Thj + q
si + Δ(i,j) ≤ sj + Tck – Tsj – q
Where
q is a constant
si are variables, simin ≤ si
Tck is a variable
Spring 2012, Feb 22 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
23
Maximum Tolerance for Given Clock
Frequency
Linear program:
Maximize q
Subject to:
For all flip-flop pairs (i,j),
si + δ(i,j) ≥ sj + Thj + q
si + Δ(i,j) ≤ sj + Tck – Tsj – q
Where
Tck is a constant
si are variables, simin ≤ si
q is a variable
Spring 2012, Feb 22 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
24
No solution because of
zero slack.
Increasing skew tolerance q
Tradeoffs
Increasing clock period Tck
Spring 2012, Feb 22 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
25
Clock Skew Problem
 N. Maheshwari and S. S. Sapatnekar, Timing

Analysis and Optimization of Sequential Circuits,
Springer, 1999.
J. P. Fishburn, “Clock Skew Optimization,” IEEE
Trans. Computers, vol. 39, no. 7, pp. 945-951,
July 1990.
Spring 2012, Feb 22 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
26