Lecture 7: Constraint Graph and Retiming Solution
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Transcript Lecture 7: Constraint Graph and Retiming Solution
ELEC 7770
Advanced VLSI Design
Spring 2010
Constraint Graph and Retiming Solution
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University
Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr10/course.html
Spring 2010, Feb 10 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
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Retiming Theorem
Given a network G(V, E, W) and a cycle time T,
(r1, . . . ) is a feasible retiming if and only if:
ri – rj ≤ wij
for all edges (vi,vj) ε E
ri – rj ≤ W(vi,vj) – 1 for all node-pairs vi, vj such that
D(vi,vj) > T
Where,
W(vi,vj) is the minimum weight path between vi and vj
D(vi,vj) is the maximum delay among all minimum
weight paths between vi and vj
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Retiming Theorem Explained
Condition 1, ri – rj ≤ wij is related to edge weight:
Original circuit is feasible => original weight wij is positive
Originally, ri = rj = 0
Retiming, rj flip-flops added to eij, ri flip-flops removed
from eij, net reduction ri – rj must be less than wij to leave
the retimed weight of eij positive.
Condition 2, ri – rj ≤ W(vi,vj) – 1 is related to path
delays between node pairs being less than clock
period T whenever path weight is 0.
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Timing Optimization
Find the clock period (T) by path analysis.
Set clock period to T/2 and find a feasible
retiming.
If feasible, further reduce the clock period to
half.
If not feasible, increase clock period.
Do a binary search for optimum clock period.
Retime the circuit.
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Representing a Constraint
ri – rj ≤ wij
rj
Spring 2010, Feb 10 . . .
or
– wij
rj ≥ ri – wij
ri
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Constraint Graph
-6
r1 ≥ r0 + 3
r1 ≥ r2 + 1
r2 ≥ r0 + 1
r2 ≥ r1 – 1
r3 ≥ r1 + 1
r3 ≥ r2 + 4
r0 ≥ r3 – 6
r1
3
1
-1
r0
1
1
r3
4
r2
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Feasibility Condition
A set of values for variables can be found if and
only if the constraint graph has no positive
cycles.
This is also the condition for the solvability of the
longest path problem, which provides a solution
to the set of constraints.
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Example: Infeasible Constraints
x2
x1 ≥ x2 + 6
x2 ≥ x1 – 3
x2 ≥ x1 – 3
6
x1
3
x2
-3
Positive cycle mean no
longest path can be found.
Spring 2010, Feb 10 . . .
x1 ≥ x2 + 6
0
3
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x1
8
Solving a Constraint Set
-6
r1 ≥ r0 + 3
r1 ≥ r2 + 1
r2 ≥ r0 + 1
r2 ≥ r1 – 1
r3 ≥ r1 + 1
r3 ≥ r2 + 4
r0 ≥ r3 – 6
r1
3
r0
Longest paths from source r0
1
to r0, r1, r2, r3
Path lengths: s0=0, s1=3, s2=2, s3=6
Solution: r0=0, r1=3, r2=2, r3=6
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1
-1
1
r3
4
r2
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The General Path Problem
Find the shortest (or longest) path in a graph
from a source vertex to all other vertices.
Graph has vertices and directed edges:
Edge weights can be positive or negative
Graph can be cyclic
Single source vertex – a vertex with 0 in-degree (not
a necessary condition)
Inconsistent problems
Negative weight cycles for shortest path
Positive weight cycles for longest path
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Dijkstra’s Shortest Path Algorithm
Greedy algorithm.
Applies to directed acyclic graphs (DAG) with positive
edge weights.
Computational complexity
O(|E| + |V| log |V|) ≤ O(n2)
References:
A. Aho, J. Hopcroft and J. Ullman, Data Structures and
Algorithms, Reading, Massachusetts: Addison-Wesley, 1983.
T. Cormen, C. Leiserson and R. Rivest, Introduction to
Algorithms, New York: McGraw-Hill, 1990.
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Dijkstra’s Shortest Path Algorithm
Example 1
w01=15
v0
source
v1
3
s0
s1
s2
s3
Initially: mark v0
0
15
2
Step 1: mark v2
0
12
2
8
Step 2: mark v3
0
11
2
8
Step 3: mark v1
0
11
2
8
v3
10
2
Alg. steps
6
v2
si = path weight (v0, vi)
Each step marks the path with smallest weight and updates the unmarked
path weights.
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Dijkstra’s Shortest Path Algorithm
Example 2
w01=15
v0
source
v1
3
s0
s1
s2
s3
Initially: mark v0
0
15
2
Step 1: mark v2
0
8
2
12
Step 2: mark v1
0
8
2
12
Step 3: mark v3
0
8
2
12
v3
6
2
Alg. steps
10
v2
si = path weight (v0, vi)
Each step marks the path with smallest weight and updates the unmarked
path weights.
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Dijkstra’s Algorithm, G(V, E, W)
s0(1) = 0
for ( i = 1 to n )
initialize source
initialize path weights, n=|V| –1
si(1) = w0i
repeat {
Select an unmarked vertex vq such that sq is minimal
Mark vq
foreach ( unmarked vertex vi )
si =
min
{ si, sq + wqi }
}
until (all vertices are marked)
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Try Dijkstra’s Algorithm for Your Graph
http://www.dgp.toronto.edu/people/JamesStewart/270/9798s/Laffra/DijkstraApplet.html
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Dijkstra’s Longest Path Algorithm
w01=15
v0
source
v1
3
v3
10
2
Either change min to max
Or change all positive weights to negatives
6
Alg. steps
s0
s1
s2
s3
Initially
0
-15 -2
Step 1: mark v1
0
-15 -2
Step 2: mark v2
0
-15 -2
-8
Step 3: mark v3
0
-15 -2
-8
v2
w01= -15
v0
source
v1
-3
v3
-10
-2
-6
v2
si = path length (v0, vi)
Spring 2010, Feb 10 . . .
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Dijkstra’s Alg. Does Not Work for
Cycles, Mixed Weights
-2
w01=15
v0
source
v1
3
s0
s1
s2
s3
Initially: mark v0
0
15
2
Step 1: mark v2
0
7
2
6
Step 2: mark v3
0
7
2
6
Step 3: mark v1
0
7
2
6?
v3
5
2
Alg. steps
4
v2
si = path weight (v0, vi)
Algorithm stops because all vertices are marked.
But, there exists a v0 to v3 path of length 5
Spring 2010, Feb 10 . . .
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Bellman’s Equations – Shortest Path
vj
vk
wki
wji
For all vertices:
vi
vm
wmi
si
wni
=
min
(sq + wqi)
vq ε pred(vi)
vn
sq =
minimum path weight between
source and vq
Spring 2010, Feb 10 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
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Bellman-Ford Algorithm, G(V, E, W)
Bellman-Ford {
s0(1) = 0
for ( i = 1 to n )
initialize source
initialize path weights, n = |V| – 1
si(1) = w0i
for ( j = 1 to n )
n iterations
for ( i = 1 to n )
si(j+1) =
min
{ si(j), sk(j) + wkj }
vk ε pred(vi)
}
if ( si(j+1) == si(j) i ) return (true)
}
return (false)
Spring 2010, Feb 10 . . .
Complexity = O(|V||E|) ≤ O(n3)
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Bellman-Ford Shortest Path
n=3
w01=15
v0
source
v1
3
s1
s2
s3
Initially
0
15
2
Iteration 1
0
12
2
8
Iteration 2
0
11
2
8
Iteration 3
0
11
2
8
6
v2
si = path weight (v0, vi)
Spring 2010, Feb 10 . . .
s0
v3
10
2
Alg. steps
ELEC 7770: Advanced VLSI Design (Agrawal)
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Bellman-Ford Longest Path
Reverse the sign of weights and solve shortest path problem.
(Alternative: keep original weights and change min operator in
algorithm to max.)
n = 3 (shortest path)
Weights reversed
w01= -15
v0
source
v1
s0
s1
s2
s3
Initially
0
-15 -2
Iteration 1
0
-15 -2
-8
Iteration 2
0
-15 -2
-8
-3
v3
-10
-2
Alg. steps
-6
v2
si = path weight (v0, vi)
Spring 2010, Feb 10 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
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Bellman’s Equations – Longest Path
vj
vk
wki
wji
For all vertices:
vi
vm
wmi
si
wni
=
max
(sq + wqi)
vq ε pred(vi)
vn
sq =
maximum path weight between
source and vq
Spring 2010, Feb 10 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
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Bellman-Ford for Cycles, Neg. Weights
w01=15
v0
source
v1
-2
3
Alg. steps
s0
s1
s2
s3
Initially
0
15
2
Iteration 1
0
7
2
6
Iteration 2
0
7
2
5
Iteration 3
0
7
2
5
v3
5
2
n = 3 (shortest path)
4
v2
si = path weight (v0, vi)
This was incorrect with Dijkstra’s shortest path algorithm
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Bellman-Ford for Negative Cycle
w01=15
v0
source
v1
-3
Alg. steps
s0
s1
s2
s3
Initially
0
15
2
Iteration 1
0
7
2
6
Iteration 2
0
3
2
6
Iteration 3
0
3
2
5
v3
5
2
n = 3 (shortest path)
2
4
v2
si = path weight (v0, vi)
Values not stabilized after n iterations.
Inconsistent problem: negative cycle.
Spring 2010, Feb 10 . . .
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Retiming Example
10
a
5
b
FF
5
c
Delay
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Retiming Graph
a
10
b
5
FF
5
c
1
h
0
0
a
10
0
b
5
1
c
5
Critical path = 15
It is the longest path consisting only of zero weight edges.
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Feasibility Constraints (Condition 1)
a
10
b
5
FF
5
c
1
h
0
0
a
10
0
b
5
ri – rj ≤ wij
edges i → j
Retiming should not cause
negative edge weights.
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c
5
rh – ra ≤ 0
ra – rb ≤ 0
rb – rc ≤ 1
rc – rh ≤ 1
27
Constraint Graph
a
10
b
5
FF
5
c
-1
rh
0
0
ra
10
0
rb
5
-1
rc
5
rh – ra ≤ 0
ra – rb ≤ 0
Constraints for
rb – rc ≤ 1
Condition 1
rc – rh ≤ 1
Observation: Constraint graph has the same structure as the original
retiming graph, with signs of weights reversed. Vertex labels are the
retiming integer variables.
ri – rj ≤ wij
edges i → j
Retiming should not cause
negative edge weights.
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Max Delay for Min Weight Paths
1
h
0
0
a
10
0
b
5
1
c
5
T = 15
W(h,a) = 0
W(h,b) = 0
W(h,c) = 1
W(a,b) = 0
W(a,c) = 1
W(a,h) = 2
Spring 2010, Feb 10 . . .
D(h,a) = 10
D(h,b) = 15
D(h,c) = 20
D(a,b) = 15
D(a,c) = 20
D(a,h) = 20
W(b,c) = 1
W(b,h) = 2
W(b,a) = 2
W(c,h) = 1
W(c,a) = 1
W(c,b) = 1
ELEC 7770: Advanced VLSI Design (Agrawal)
D(b,c) = 10
D(b,h) = 10
D(b,a) = 20
D(c,h) = 5
D(c,a) = 15
D(c,b) = 20
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Timing Optimization, T = 7.5?
-1
rh
0
0
ra
10
0
Add constraints for
Condition 2:
ri – rj ≤ W(I,j) – 1
W(h,a) = 0
W(h,b) = 0
W(h,c) = 1
W(a,b) = 0
W(a,c) = 1
W(a,h) = 2
Spring 2010, Feb 10 . . .
D(h,a) = 10
D(h,b) = 15
D(h,c) = 20
D(a,b) = 15
D(a,c) = 20
D(a,h) = 20
Constraint graph
(feasibility)
rb
5
-1
rc
5
paths (i,j) such that D(i,j) > 7.5
W(b,c) = 1
W(b,h) = 2
W(b,a) = 2
W(c,h) = 1
W(c,a) = 1
W(c,b) = 1
ELEC 7770: Advanced VLSI Design (Agrawal)
D(b,c) = 10
D(b,h) = 10
D(b,a) = 20
D(c,h) = 5
D(c,a) = 15
D(c,b) = 20
30
Timing Optimization, T = 7.5?
-1
0
-1
-1
W(h,a) = 0
W(h,b) = 0
W(h,c) = 1
W(a,b) = 0
W(a,c) = 1
W(a,h) = 2
Spring 2010, Feb 10 . . .
1
1
1
rh
0
Positive cycle;
no solution for
longest path
0
0
ra
10
-1
0
rb
5
-1
0
rc
5
0
0
D(h,a) = 10
D(h,b) = 15
D(h,c) = 20
D(a,b) = 15
D(a,c) = 20
D(a,h) = 20
W(b,c) = 1
W(b,h) = 2
W(b,a) = 2
W(c,h) = 1
W(c,a) = 1
W(c,b) = 1
ELEC 7770: Advanced VLSI Design (Agrawal)
D(b,c) = 10
D(b,h) = 10
D(b,a) = 20
D(c,h) = 5
D(c,a) = 15
D(c,b) = 20
31
Timing Optimization, T = 11.25?
-1
1
1
rh
0
0
-1
0
ra
10
0
-1
0
rb
5
-1
rc
5
rh = 0
rb = 1
rc = 0
ra = 0
0
0
W(h,a) = 0
W(h,b) = 0
W(h,c) = 1
W(a,b) = 0
W(a,c) = 1
W(a,h) = 2
Spring 2010, Feb 10 . . .
D(h,a) = 10
D(h,b) = 15
D(h,c) = 20
D(a,b) = 15
D(a,c) = 20
D(a,h) = 20
W(b,c) = 1
W(b,h) = 2
W(b,a) = 2
W(c,h) = 1
W(c,a) = 1
W(c,b) = 1
ELEC 7770: Advanced VLSI Design (Agrawal)
D(b,c) = 10
D(b,h) = 10
D(b,a) = 20
D(c,h) = 5
D(c,a) = 15
D(c,b) = 20
32
Retiming Graph
a
10
b
5
FF
5
c
1
h
0
rh = 0
0
a
10
ra = 0
0
1
b
5
1
0
rb = 1
c
5
rc = 0
wij_retimed = wij + rj – ri
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Retimed Circuit
a
10
FF
b
5
Logic optimization
will remove these.
1
h
0
rh = 0
0
a
10
ra = 0
1
5
c
b
5
0
rb = 1
c
5
rc = 0
Critical Path = 10
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Reference
G. De Micheli, Synthesis and Optimization
of Digital Circuits, New York: McGraw-Hill,
1994.
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