Transcript Lecture 21: Soft Errors and Fault-Tolerant Design

ELEC 7770
Advanced VLSI Design
Spring 2007
Soft Errors and Fault-Tolerant Design
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University
Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07
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Soft Errors
 Soft errors are the errors caused by the



operating environment.
They are not due to a permanent hardware fault.
Soft errors are intermittent or random, which
makes their testing unreliable.
One way to deal with soft errors is to make
hardware robust:
 Capable of detecting soft errors
 Capable of correcting soft errors
 Both measures are probabilistic
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Some Early References
 J. von Neumann, “Probabilistic Logics and the Synthesis


of Reliable Organisms from Unreliable Components,” pp.
329-378, 1959, in A. H. Taub, editor, John von Neumann:
Collected Works, Volume V: Design of Computers,
Theory of Automata and Numerical Analysis,
Oxford University Press, 1963.
M. A. Breuer, “Testing for Intermittent Faults in Digital
Circuits,” IEEE Trans. Computers, vol. C-22, no. 3, pp.
241-246, March 1973.
T. C. May and M. H. Woods, “Alpha-Particle-Induces Soft
Errors in Dynamic Memories,” IEEE Trans. Electron
Devices, vol. ED-26, no. 1, pp. 2-9, 1979.
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Causes of Soft Errors
 Interconnect coupling (crosstalk).
 Power supply noise: IR-drop, delta-I.
 Effects generally attributed to alpha-particles:
 Charged particles: electrons, protons, ions.
 Radiation (photons): X-rays, gamma-rays, ultra-violet
light.
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Sources of Alpha-Particles
 Radioactive contamination in VLSI packaging


material.
Ionosphere, magnetosphere and solar radiation.
Other electromagnetic radiation.
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Alpha-Particle
 Helium nucleus: two protons and two

neutrons, mass = 6.65 ×10-27kg, charge =
+2e (e = 1.6 ×10-19C).
Energy = 3.73 GeV
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Soft Error Rate (SER)
 Failures in time (FIT): One FIT is 1 error per

billion hours of operation.
Alternative unit is mean time between failures
(MTBF).
1 year MTBF
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=
109/(365×24) = 114,155 FIT
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Particle Strike
Ion or
Charged particle
- +
n + +
+ - p - substrate
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current
Induced Current
time
I(t) = I0(e– t/a – e– t/b),
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a >> b
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Voltage Induced at a Node
V = Q/C
Where Q = ∫ I(t) dt
C = node capacitance
Smaller node capacitance will result in
larger voltage swing.
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Effect on Digital Circuit
Charged
Particles
IN
Charged
Particles
Combinational
Logic
OUT
CK
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An SRAM Cell
WL
VDD
0
bit
1
bit
BL
BL
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SRAM Cell Struck by Alpha-Particle
Single-Event Upset (SEU)
WL
Charged
Particles
VDD
0→1
bit
1→0
bit
BL
BL
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D-Latch
1
D
CK = 0
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Q
0
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SEU in D-Latch
1→0
Q
D
CK = 0
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Charged
Particles
0→1
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Single Event Transients in
Combinational Logic
1
0
1
1
1
CK
Charged
Particles
0
CK
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Effects of Transients
 Error correcting effects

 Transient pulse is filtered by gate inertia
 Transient is blocked by an unsensitized path
 Transient is blocked by an inactive clock
Error enhancing effects
 Large number of gates can produce multiple
pulses
 Fanouts can multiply error pulses
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SEUs in FPGA
 Parts that can be affected




Look-up table (LUT)
Configuration memory cell
Flip-flop
Block RAM
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F1
F2
F3
F4
LUT
1
1
1
Memory cells
0
0
1
0
0
0
out
0
1
1
1
0
0
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F1
F2
F3
1
1
1
F4
SEU in
LUT
Memory cells
0
0
Charged
Particle
1 changed
to 0
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1
0
0
0
out
0
1
1
0
0
0
1
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Four Types of SEU in FPGA
M
M M M M
FF
F1
F2
F3
F4
M
Type 3
Type 2
LUT
Type 1
M
Configuration
memory
cell
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Type 4
ELEC 7770: Advanced VLSI Design (Agrawal)
Block
RAM
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SEU Detection Methods




Hardware redundancy
Time redundancy
Error detection codes (EDC)
Self-checker techniques
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SEU Mitigation Techniques





Triple modular redundancy (TMR)
Multiple redundancy with voting
Error detection and correction codes (EDAC)
Hardened memory cells
FPGA-specific methods
 Reconfiguration
 Partial configuration
 Rerouting design
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Hardware Redundancy for Detection
inputs
Combinational
Logic
Combinational
Logic
(duplicated)
output
Logic 1
indicates
error
Hardware overhead is high ~ 100%
Performance penalty is negligible.
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Time Redundancy for Detection
inputs
Combinational
Logic
DQ
output
CK+ d
DQ
Logic 1
indicates
error
CK
Hardware overhead is low.
Performance penalty ( ~ d) = maximum detectable pulse width.
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Repeat on Error Detection
inputs
Combinational
Logic
DQ
C
output
CK+ d
DQ
Logic 1
indicates
error
CK
Operation:
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If error is detected, then output retains its previous value.
Repeating the computation can produce correct result.
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Muller C-Element
A
output
C
B
A
B
output
A
0
0
0
0
1
Old output
1
0
Old output
1
1
1
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B
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S Q
output
R
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Triple Modular Redundancy (TMR)
Combinational
Logic copy 1
inputs
Combinational
Logic copy 2
Majority
Voter
output
Combinational
Logic copy 3
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Majority Voter Circuit
A
0
B
0
C
0
output
A
0
B
C
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
0
1
0
1
1
1
1
0
1
1
1
1
1
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Majority
Voter
output
A
B
output
C
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Alternative Implementations of Voter
VDD
A
LUT
0
0
0
1
0
1
1
1
output
B
output
C
ABC
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Triple Modular Redundancy (TMR)
inputs
Combinational
Logic
DQ
CK
DQ
Majority
Voter
CK+ d
DQ
output
CK+3d
DQ
CK+2d
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TMR for Memory Cells
inputs
Combinational
Logic
DQ
CK
DQ
Majority
Voter
output
CK
DQ
CK
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Problems:
1. Accumulation of
errors in flip-flops.
1. Voter is not protected.
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FF Refresh and TMR for Memory Cells
r1
DQ
r2
CK
Majority
Voter
DQ
r3
Majority
Voter
CK
Majority
Voter
output
DQ
CK
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Majority
Voter
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A Resistor Hardened SRAM Cell
WL
VDD
0
bit
1
bit
BL
BL
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References
 F. L. Kastensmidt, L. Carro and R. Reis, Fault
Tolerant Techniques for SRAM-Based FPGAs,
Springer, 2006.
S. Mitra, N. Seifert, M. Zhang, Q. Shi, and K. S.
Kim, “Robust System Design with Built-In SoftError Resilience,” Computer, vol. 38, no. 2, pp.
43-52, February 2005.
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Summary of Topics Covered (1)
 Nanotechnology devices
 Moore’s law
 System level design for testability and test scheduling


problem
Verification
 Logic equivalence
 Binary decision diagrams
Power consumption and low-power concepts
 Multi-core parallelism
 Microprocessors
 Memories
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Summary of Topics Covered (2)
 Timing
 Timing verification
 Timing simulation
 Static timing analysis
 Timing optimization
 Linear programming and clock constraints
 Clock skew problem
 Zero skew design
 Retiming, constraint graph and performance
optimization
 Soft errors and fault-tolerant design
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