Transcript Lecture 18: Zero-Skew Design

ELEC 7770
Advanced VLSI Design
Spring 2007
Zero-Skew Design
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University
Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07
Spring 07, Apr 3
ELEC 7770: Advanced VLSI Design (Agrawal)
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Zero-Skew Clock Routing
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CK
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Zero-Skew: References
 H-Tree
 A. L. Fisher and H. T. Kung, “Synchronizing Large
Systolic Arrays,” Proc. SPIE, vol. 341, pp. 44-52,
May 1982.
 A. Kahng, J. Cong and G. Robins, “HigPerformance Clock Routing Based on Recursive
Geomrtric Matching,” Proc. Design Automation
Conf., June 1991, pp. 322-327.
 M. A. B. Jackson, A. Srinivasan and E. S. Kuh,
“Clock Routing for High-Performance IC’s,” Proc.
Design Automation Conf., June 1990, pp. 573-579.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Zero-Skew Routing
 Build clock tree bottom up:
 Leaf nodes are all equal loading flip-flops.
 Two zero-skew subtrees are joined to form a larger zero-skew
subtree.
 Entire clock tree is built recursively.
 R.-S. Tsay, “An Exact Zero-Skew Clock Routing

Algorithm,” IEEE Trans. CAD, vol. 12, no. 2, pp. 242249, Feb. 1993.
J. Rubenstein, P. Penfield and M. A. Horowitz, “Signal
Delay in RC Tree Networks,” IEEE Trans. CAD, vol. 2,
no. 3, pp. 202-211, July 1983.
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Balancing Subtrees (1)
xL
r1
c1/2
A
c1/2
t1
C1
Subtree 1
Tapping point
(1 – x)L
r2
c2/2
B
c2/2
t2
C2
Subtree 2
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Balancing Subtrees (2)
 Subtrees 1 and 2 are each balanced (zero


skew) trees, with delays t1 and t2 to respective
leaf nodes.
Total capacitances of subtrees are C1 and C2,
respectively.
Connect points A and B by a minimum-length
wire of length L.
Determine a tapping point x such that wire
lengths xL and (1 – x)L produce zero skew.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Balancing Subtrees (3)
 Use Elmore delay formula:

r1(C1 + c1/2) + t1 = r2(C2 + c2/2) + t2
Substitute:
 r1 = axL, r2 = a(1 – x)L
 c1 = bxL, c2 = b(1 –x)L
abL2x + (C1+C2)x = (t2 – t1) + aL(C2+bL/2)
 Then solve for x:
(t2 – t1) + aL (C2 + bL/2)
x = ────────────────
aL(bL + C1 + C2)
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Balancing Subtrees Example 1
 Subtree parameters:


x
 Subtree 1: t1 = 5ps, C1 = 3pF
 Subtree 2: t2 = 10ps, C2 = 6pF
Interconnect:
 L = 1mm
 Wire parameters: a = 100Ω/cm, b = 1pF/cm
Tapping point:
=
(t2 – t1) + aL (C2 + bL/2)
────────────────
aL (bL + C1 + C2)
=
(10–5) + 100×0.1(6 + 1×0.1/2)
──────────────────
100×0.1(1×0.1+3+6)
= (5 + 60.5)/(10×9.1) = 0.7198
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Example 1
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0.7198mm
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FF
Subtree 1
FF
To next
level
FF
0.2802mm
FF
Subtree 2
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Balancing Subtrees, x > 1
 Tapping point set at root of tree with larger loading (C2, t2).
 Wire to the root of other tree is elongated to provide



additional delay. Wire length L found as follows:
Set x = 1 in abL2x + (C1+C2)x = (t2 – t1) + aL(C2+bL/2)
i.e., L2 + (2C1/b)L – 2(t2 – t1)/(ab) = 0
Wire length is given by:
[(aC1)2+2ab(t2 – t1)]½ – aC1
L
=
──────────────────
ab
R.-S. Tsay, “An Exact Zero-Skew Clock Routing Algorithm,”
IEEE Trans. CAD, vol. 12, no. 2, pp. 242-249, Feb. 1993.
Spring 07, Apr 3
ELEC 7770: Advanced VLSI Design (Agrawal)
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Balancing Subtrees Example 2
 Subtree parameters:


x
 Subtree 1: t1 = 2ps, C1 = 1pF
 Subtree 2: t2 = 15ps, C2 = 10pF
Interconnect:
 L = 1mm
 Wire parameters: a = 100Ω/cm, b = 1pF/cm
Tapping point:
=
(t2 – t1) + aL (C2 + bL/2)
────────────────
aL (bL + C1 + C2)
=
(15–2) + 100×0.1(10 + 1×0.1/2)
──────────────────
100×0.1(1×0.1+1+10)
= (13 + 100.5)/(10×11.1) = 1.0225
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Example 2, x = 1.0225
L
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=
[(aC1)2+2ab(t2 – t1)]½ – aC1
──────────────────
ab
=
[(100×1)2+2100×1(15 – 2)]½ – 100×1
───────────────────────
100×1
=
0.1225cm
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Example 2, L = 1.255mm
FF
FF
L = 1.225mm
FF
Subtree 1
FF
FF
To next
level
FF
Subtree 2
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Balancing Subtrees, x < 1
 Tapping point set at root of tree with smaller loading (C1, t1).
 Wire to the root of other tree is elongated to provide



additional delay. Wire length L found as follows:
Set x = 0 in abL2x + (C1+C2)x = (t2 – t1) + aL(C2+bL/2)
i.e., L2 + (2C2/b)L – 2(t1 – t2)/(ab) = 0
Wire length is given by:
[(aC2)2+2ab(t1 – t2)]½ – aC2
L
=
──────────────────
ab
R.-S. Tsay, “An Exact Zero-Skew Clock Routing Algorithm,”
IEEE Trans. CAD, vol. 12, no. 2, pp. 242-249, Feb. 1993.
Spring 07, Apr 3
ELEC 7770: Advanced VLSI Design (Agrawal)
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Balancing Subtrees Example 3
 Subtree parameters:


x
 Subtree 1: t1 = 15ps, C1 = 10pF
 Subtree 2: t2 = 2ps, C2 = 1pF
Interconnect:
 L = 1mm
 Wire parameters: a = 100Ω/cm, b = 1pF/cm
Tapping point:
=
(t2 – t1) + aL (C2 + bL/2)
────────────────
aL (bL + C1 + C2)
=
(2–15) + 100×0.1(1 + 1×0.1/2)
──────────────────
100×0.1(1×0.1+1+10)
= ( – 13 + 10.5)/(10×11.1) = – 0.0225
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Example 3, x = – 0.0225
L
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=
[(aC2)2+2ab(t1 – t2)]½ – aC2
──────────────────
ab
=
[(100×1)2+2100×1(15 – 2)]½ – 100×1
───────────────────────
100×1
=
0.1225cm
ELEC 7770: Advanced VLSI Design (Agrawal)
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Example 3, L = 1.255mm
FF
FF
To next
level
FF
L = 1.225mm
FF
Subtree 1
FF
FF
Subtree 2
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Zero-Skew Design
Delay
=75ns
Delay
= 50ns
Comb.
Comb.
FF A
FF B
FF C
CK
CK
Tck = 75ns
time
Single-cycle path delay
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Nonzero-Skew Design
Delay
=75ns
Delay
= 50ns
Comb.
Comb.
FF A
FF B
FF C
CK
Delay = 25ns
CK
Tck = 50ns
time
Single-cycle path delay
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Conclusion
 Zero-skew design is possible at the layout level.
 Zero-skew usually results in higher clock speed.
 Nonzero clock skews can improve the design
with reduced hardware and/or higher speed.
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