Transcript Lecture 17: Clock Skew Problem

ELEC 7770
Advanced VLSI Design
Spring 2007
Clock Skew Problem
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University
Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07
Spring 07, Mar 22
ELEC 7770: Advanced VLSI Design (Agrawal)
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Single Clock
Data_in
Data_out
Comb.
FF A
FF B
CKA
CKB
CK
CKA
CKB
Single-cycle path delay
Spring 07, Mar 22
ELEC 7770: Advanced VLSI Design (Agrawal)
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Multiple Clocks
Data_in
Data_out
Comb.
FF A
CKA
FF B
CKB
CKA
CKB
Multi-cycle path delay
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Clock Skew
 Skew is the time delay of clock signal at a flip

flop with respect to some time reference.
For a given layout each flip-flop has a skew,
measured with respect to the a common
reference.
Skews of flip-flops separated by combinational
paths affect the short-path and long-path
constraints.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Skews for Single-Cycle Paths
FFi
CKi
Combinational
Block
Delay:
δ(i,j) ≤ d(i,j) ≤ Δ(i,j)
xi
FFj
CKj
xj
xi and xj are arrival times of clock edges
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Short-Path Constraint (Double-Clocking)
Tck
CKi
xi
Not intended
CKj
intended
Thj
xj
δ(i,j)
xi + δ(i,j) ≥ xj + Thj
Spring 07, Mar 22
ELEC 7770: Advanced VLSI Design (Agrawal)
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Long-Path Constraint (Zero-Clocking)
Tck
CKj
xi
intended
Not intended
CKi
xj
Tsj
Δ(i,j)
xi + Δ(i,j) ≤ xj + Tck – Tsj
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Maximum Clock Frequency
Linear program:
Minimize Tck
Subject to:
For all flip-flop pairs (i,j),
xi + δ(i,j) ≥ xj + Thj
xi + Δ(i,j) ≤ xj + Tck – Tsj
Spring 07, Mar 22
ELEC 7770: Advanced VLSI Design (Agrawal)
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Finding Clock Skews
xk
xi
FFi
Ri
FFj
Rj
FFk
Rk
CK
Ci
Cj
Ck
xj
Use Elmore delay formula to calculate xi, xj, xk.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Interconnect Delay: Elmore Delay Model
 W. Elmore, “The Transient Response of Damped Linear Networks with
Particular Regard to Wideband Amplifiers,” J. Appl. Phys., vol. 19,
no.1, pp. 55-63, Jan. 1948.
Ri
i
Rj
CK
Shared resistance:
Rii = Ri
Rij = Rji = Ri
Rik = Rki = Ri
Rjj = Ri + Rj
Rjk = Rkj = Ri + Rj
Rkk = Ri + Rj + Rk
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Ci
Rk
j
Cj
ELEC 7770: Advanced VLSI Design (Agrawal)
k
Ck
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Elmore Delay Calculation
Delay at node k,
xk
= 0.69 (Ci × Rik + Cj × Rjk + Ck × Rkk )
= 0.69 [Ri Ci + (Ri+Rj) Cj + (Ri+Rj+Rk)Ck]
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Finding δ(I,j) and Δ(I,j)
Minimum delay
Maximum delay
, -
, -
A
1
, -
, -
0, 0
B
3
3, 3
i
, -
, -
, -
, -
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C
1
D
2
E
1
j
J 5, 6
1
k
4, 4
G
2
, -
, -
H 6, 6
3
F
1
5, 5
ELEC 7770: Advanced VLSI Design (Agrawal)
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Maximum Clock Frequency for
Tolerance ±q/2 in Skew
Linear program:
Minimize Tck
Subject to:
For all flip-flop pairs (i,j),
xi + δ(i,j) ≥ xj + Thj + q
xi + Δ(i,j) ≤ xj + Tck – Tsj – q
Where q is a constant.
Spring 07, Mar 22
ELEC 7770: Advanced VLSI Design (Agrawal)
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Maximum Tolerance for Given Clock
Frequency
Linear program:
Maximize q
Subject to:
For all flip-flop pairs (i,j),
xi + δ(i,j) ≥ xj + Thj + q
xi + Δ(i,j) ≤ xj + Tck – Tsj – q
Where Tck is a constant.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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No solution because of
Zero slack.
Increasing skew tolerance q
Tradeoffs
Increasing clock period Tck
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Clock Skew Problem
 N. Maheshwari and S. S. Sapatnekar, Timing

Analysis and Optimization of Sequential Circuits,
Springer, 1999.
J. P. Fishburn, “Clock Skew Optimization,” IEEE
Trans. Computers, vol. 39, no. 7, pp. 945-951,
July 1990.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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