Transcript Lecture 14: Timing Verification and Optimization

ELEC 7770
Advanced VLSI Design
Spring 2007
Timing Verification and Optimization
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University
Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07
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Proof of Correctness
 Static timing analysis proves the timing



correctness. That is, the circuit is guaranteed to
work at the clock rate determined by the critical
path.
But the circuit may also work correctly at faster
speeds.
Because the critical path identified by STA may
be a “false path”.
STA overestimates the delay of the circuit.
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False and True Paths
 A false path cannot propagate an event and hence

cannot affect the timing of the circuit. False paths are
dynamically unsensitizable.
Dynamically sensitizable path (true path): All off-path
inputs must settle down to their non-controlling values
when the event propagates through the path.
a
b
c
1
0
d 1
True path of length 3
e
y
2
1
f
1
1
3
z
1
0
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True path of
length 4
3
Static Sensitization of Path
 Static sensitization of path: All off-path inputs can

be set to their non-controlling values.
Longest path in the following example is statically
unsensitizable. Such paths are often referred to,
though not correctly, as false paths.
True path of length 3
a
1
d 1
e
2
1
1
b
0
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1
y
1
3
f
ELEC 7770: Advanced VLSI Design (Agrawal)
z
1
4
False path of
length 4
4
An Example
 A statically unsensitizable false path can be dynamically

sensitizable.
P. C. McGeer and R. K. Brayton, Integrating Functional and
Temporal Domains in Logic Design, Springer, 1991.
a
False paths of delay 3
e
1
1
1
g
d
b
c
1
1
f
0
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Static Sensitization Condition
x
y
z
Off-path inputs
There must exist an input vector (PI) that satisfies the following conditions:
∂y/∂x = 1, ∂z/∂y = 1, . . .
Where ∂y/∂x = y(x=1, PI)  y(x=0, PI) is Boolean difference
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An ATPG Method
x
y
z
Stuck-at-0
Path is false if this
fault is redundant
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Optimism and Pessimism
Statically
Dynamically
sensitizable
sensitizable
Paths
paths
(optimistic)
Structural paths analyzed by STA (pessimistic)
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Theorem
 Every statically sensitizable path is dynamically


sensitizable.
Proof: Since a vector exists to sensitize the path,
if that vector does not specify the path input,
then toggling the primary input at the origin of
the path will propagate an event through the
path.
P. C. McGeer and R. K. Brayton, Integrating
Functional and Temporal Domains in Logic
Design, Springer, 1991, p. 35.
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Theorem
 Longest path in a circuit is dynamically


sensitizable if it is statically sensitizable.
Proof: Because this is the longest path, all offpath inputs will settle to their sensitizing values
at the inputs of any gate before the on-path
event propagates through that gate.
P. C. McGeer and R. K. Brayton, Integrating
Functional and Temporal Domains in Logic
Design, Springer, 1991, p. 37.
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Speeding Up a Circuit
2
w
a
x
2
w
a
3
u
2
2
v
2
y
z
u
v
x
y
z
0 1 2 3 4 5 6 7 time
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Speeding Up a Circuit
Reducing the delay of a false path can increase circuit delay.
2
w
a
x
2
w
a
1
u
2
2
v
2
y
z
u
v
x
y
z
0 1 2 3 4 5 6 7 time
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A Delay Optimization Algorithm
 REDUCE_DELAY(Circuit graph (V, E), ε)
Repeat {
Compute critical paths and critical delay Δ
Set output data ready time to Δ
Compute slacks
U = vertex subset with slack < ε
W = select vertices in U
Apply transformation to vertices in W
} until (no transformation can reduce Δ)

}
G. De Micheli, Synthesis and Optimization of Digital
Circuits, McGraw-Hill, 1994, p. 427.
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Example of a Transformation (1)
a
b
c
2
1
2
delay=3
d
e
g
2
1
x
2
1
y
2
Δ = 11
x = a’ + b’ + c’ + d’ + e’
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Example of a Transformation (2)
d
delay=3
b
c
a
e
2
1
2
1
2
1
2
1
x
2
y
2
g
Δ=8
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32-bit Ripple-Carry Adder
c0
a0
b0
sum0
FA0
a1
b1
sum1
FA1
a2
b2
sum2
FA2
sum31
a31
b31
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FA31
c31
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One-bit Full-Adder Circuit
ci
ai
bi
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FAi
XOR
AND
sumi
XOR
AND
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OR
Ci+1
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Speeding Up the Adder
b0-b15
cin
a16-a31
b16-b31
0
a16-a31
b16-b31
1
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16-bit
ripple
carry
adder
16-bit
ripple
carry
adder
16-bit
ripple
carry
adder
sum0-sum15
0
1
Multiplexer
a0-a15
sum16-sum31, c31
This is a carry-select adder
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