Transcript Lecture 12: Power Consumption in a Memory

ELEC 7770
Advanced VLSI Design
Spring 2007
Power Consumption in a Memory
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University
Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07
Spring 07, Feb 27
ELEC 7770: Advanced VLSI Design (Agrawal)
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Memory Architecture
M bits
Word N-2
Word N-1
SN-1
k = log2N
Input-Output (M bits)
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Word 0
Word 1
Word 2
N words
A0
A1
.
Ak-1
Decoder
Storage
cell
k address lines
Word 0
Word 1
Word 2
N words
S0
S0
M bits
SN-1
Storage
cell
Word N-2
Word N-1
Input-Output (M bits)
ELEC 7770: Advanced VLSI Design (Agrawal)
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Memory Organization
2L-K
Bit line
Storage cell
AK
AK-1
Word line
AL-1
M.2K
Sense amplifiers/drivers
A0
AK-1
Column decoder
Input-Output (M bits)
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ELEC 7770: Advanced VLSI Design (Agrawal)
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An SRAM Cell
WL
VDD
bit
bit
BL
BL
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Read Operation
1. Precharge to VDD
2. WL = Logic 1
WL
VDD
bit
bit
BL
BL
3. Sense amplifier converts BL swing to logic level
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Precharge Circuit
VDD
WL
VDD
bit
BL
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VDD
PC
bit
BL
Diff. sense ampl.
ELEC 7770: Advanced VLSI Design (Agrawal)
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Reading 1 from Cell
BL
BL
Precharge
WL
Sense ampl.
output
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time
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Write Operation, bit = 1→ 0
2. WL = 1
WL
VDD
bit
bit
BL
BL
1
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0
1. Set BL = 0, BL = 1
ELEC 7770: Advanced VLSI Design (Agrawal)
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Cell Array Power Management
 Smaller transistors
 Low supply voltage
 Lower voltage swing (0.1V – 0.3V for SRAM)
 Sense amplifier restores the full voltage swing for
outside use.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Sense Amplifier
VDD
bit
Sense ampl. enable:
Low when bit lines
are precharged and
equalized
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bit
Full voltage
swing
output
SE
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Block-Oriented Architecture
 A single cell array may contain 64 Kbits to 256


Kbits.
Larger arrays become slow and consume more
power.
Larger memories are block oriented.
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Hierarchical Organization
Block 0
Block 1
Block P-1
Row
addr.
Column
addr.
Block
addr.
Global data bus
Control
circuitry
Global amplifier/driver
Block selector
I/O
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Power Saving
 Block-oriented memory
 Lengths of local word and bit lines are kept small.
 Block address is used to activate the addressed

block.
Unaddressed blocks are put in power-saving mode:
 sense amplifier and row/column decoders are
disabled.
 Power is maintained for data retention in cells.
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1.3μ
8-kbit SRAM
1.1μ
900n
0.13μ CMOS
700n
500n
300n
0.18μ CMOS
100n
0.0
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7x increase
Leakage current (Amperes)
Static Power
0.6
1.2
1.8
Supply voltage
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Adding Resistance in Leakage Path
VDD
Low-threshold transistor
sleep
VDD.int
SRAM
cell array
SRAM
cell array
SRAM
cell array
VSS.int
sleep
GND
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Lowering Supply Voltage
VDD
Sleep = 1, data
retention mode
VDDL= 100mV for 0.13μ CMOS
sleep
SRAM
cell array
SRAM
cell array
SRAM
cell array
GND
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Parallelization of Memories
Mem 1
Mem 2
instr. A
instr. C
instr. E
.
.
.
instr. B
instr. D
instr. F Power = C’ f/2 V 2
DD
.
.
.
f/2
f/2
f/2
0
MUX
1
C. Piguet, “Circuit and Logic Level Design,” pp. 124-125 in
W. Nebel and J. Mermet (Eds.), Low Power Design in Deep
Submocron Electronics, Springer, 1997.
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References
 K. Itoh, VLSI Memory Chip Design, Springer
Verlag, 2001.
J. M. Rabaey, A. Chandrakasan and B. Nikolić,
Digital Integrated Circuits, Upper Saddle River,
New Jersey: Pearson Education, Inc., 2003.
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