Transcript Lecture 9: Power Dissipation in CMOS Chips

ELEC 7770
Advanced VLSI Design
Spring 2007
Power Dissipation in VLSI Chips
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University
Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07
Spring 07, Feb 15
ELEC 7770: Advanced VLSI Design (Agrawal)
1
ISSCC, Feb. 2001, Keynote
“Ten years from now,
microprocessors will run at
10GHz to 30GHz and be capable
of processing 1 trillion operations
per second – about the same
number of calculations that the
world's fastest supercomputer
can perform now.
Patrick P. Gelsinger
Senior Vice President
General Manager
Digital Enterprise Group
INTEL CORP.
Spring 07, Feb 15
“Unfortunately, if nothing
changes these chips will produce
as much heat, for their
proportional size, as a nuclear
reactor. . . .”
ELEC 7770: Advanced VLSI Design (Agrawal)
2
VLSI Chip Power Density
Sun’s
Surface
Power Density (W/cm2)
10000
Rocket
Nozzle
1000
Nuclear
Reactor
100
Hot Plate
8086
10 4004
8008 8085
386
286
8080
1
1970
Spring 07, Feb 15
1980
P6
Pentium®
486
1990
Year
Source: Intel
2000
ELEC 7770: Advanced VLSI Design (Agrawal)
2010
3
SIA Roadmap for Processors (1999)
Year
1999
2002
2005
2008
2011
2014
Feature size (nm)
180
130
100
70
50
35
Logic transistors/cm2
6.2M
18M
39M
84M
180M
390M
Clock (GHz)
1.25
2.1
3.5
6.0
10.0
16.9
Chip size (mm2)
340
430
520
620
750
900
Power supply (V)
1.8
1.5
1.2
0.9
0.6
0.5
High-perf. Power (W)
90
130
160
170
175
183
Source: http://www.semichips.org
Spring 07, Feb 15
ELEC 7770: Advanced VLSI Design (Agrawal)
4
Recent Data
Source: http://www.eetimes.com/story/OEG20040123S0041
Spring 07, Feb 15
ELEC 7770: Advanced VLSI Design (Agrawal)
5
Low-Power Design
 Design practices that reduce power consumption at least


by one order of magnitude; in practice 50% reduction is
often acceptable.
Low-power design methods:
 Algorithms and architectures
 High-level and software techniques
 Gate and circuit-level methods
 Test power
ELEC 6270: Low-Power Design of Electronic Circuits,
generally offered in the fall semester; course discusses
power dissipation mechanism in CMOS devices, power
optimization methods, power analysis, and system level
power optimization.
Spring 07, Feb 15
ELEC 7770: Advanced VLSI Design (Agrawal)
6
VLSI Building Blocks






Finite-state machine (FMS)
Bus
Flip-flops and shift registers
Memories
Datapath
Processors
Spring 07, Feb 15
ELEC 7770: Advanced VLSI Design (Agrawal)
7
State Encoding for a Counter
 Two-bit binary counter:


 State sequence, 00 → 01 → 10 → 11 → 00
 Six bit transitions in four clock cycles
 6/4 = 1.5 transitions per clock
Two-bit Gray-code counter
 State sequence, 00 → 01 → 11 → 10 → 00
 Four bit transitions in four clock cycles
 4/4 = 1.0 transition per clock
Gray-code counter is more power efficient.
G. K. Yeap, Practical Low Power Digital VLSI Design, Boston:
Kluwer Academic Publishers (now Springer), 1998.
Spring 07, Feb 15
ELEC 7770: Advanced VLSI Design (Agrawal)
8
Binary Counter: Original Encoding
Present
state
Next
state
a
b
A
B
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
A = a’b + ab’
B = a’b’ + ab’
Spring 07, Feb 15
a
A
b
B
CK
CLR
ELEC 7770: Advanced VLSI Design (Agrawal)
9
Binary Counter: Gray Encoding
Present
state
Next
state
a
b
A
B
0
0
0
1
0
1
1
1
1
0
0
0
1
1
1
0
A = a’b + ab
B = a’b’ + a’b
Spring 07, Feb 15
a
A
B
b
CK
CLR
ELEC 7770: Advanced VLSI Design (Agrawal)
10
Three-Bit Counters
Binary
Gray-code
State
No. of toggles
State
No. of toggles
000
-
000
-
001
1
001
1
010
2
011
1
011
1
010
1
100
3
110
1
101
1
111
1
110
2
101
1
111
1
100
1
000
3
000
1
Av. Transitions/clock = 1.75
Spring 07, Feb 15
Av. Transitions/clock = 1
ELEC 7770: Advanced VLSI Design (Agrawal)
11
N-Bit Counter: Toggles in Counting Cycle
 Binary counter: T(binary) = 2(2N – 1)
 Gray-code counter: T(gray) = 2N
 T(gray)/T(binary) = 2N-1/(2N – 1) → 0.5
Bits
T(binary)
T(gray)
T(gray)/T(binary)
1
2
2
1.0
2
6
4
0.6667
3
14
8
0.5714
4
30
16
0.5333
5
62
32
0.5161
6
126
64
0.5079
∞
-
-
0.5000
Spring 07, Feb 15
ELEC 7770: Advanced VLSI Design (Agrawal)
12
FSM State Encoding
Transition
probability
based on
PI statistics
0.6
11
0.3
0.4
00
0.6
0.6
0.1
01
0.3
0.1
0.4
01
00
0.9
0.6
0.1
0.1
11
0.9
Expected number of state-bit transitions:
2(0.3+0.4) + 1(0.1+0.1) = 1.6
1(0.3+0.4+0.1) + 2(0.1) = 1.0
State encoding can be selected using a power-based cost function.
Spring 07, Feb 15
ELEC 7770: Advanced VLSI Design (Agrawal)
13
FSM: Clock-Gating
 Moore machine: Outputs depend only on the
state variables.
 If a state has a self-loop in the state transition graph
(STG), then clock can be stopped whenever a selfloop is to be executed.
Xi/Zk
Si
Sk
Sj
Spring 07, Feb 15
Xj/Zk
Xk/Zk
Clock can be stopped
when (Xk, Sk) combination
occurs.
ELEC 7770: Advanced VLSI Design (Agrawal)
14
Clock-Gating in Moore FSM
Flip-flops
PI
Clock
activation
logic
CK
Spring 07, Feb 15
Latch
Combinational
logic
PO
L. Benini and G. De Micheli,
Dynamic Power Management,
Boston: Springer, 1998.
ELEC 7770: Advanced VLSI Design (Agrawal)
15
Bus Encoding for Reduced Power
 Example: Four bit bus
 0000 → 1110 has three transitions.
 If bits of second pattern are inverted, then 0000 → 0001 will
have only one transition.
Number of bit transitions
after inversion encoding
 Bit-inversion encoding for N-bit bus:
Spring 07, Feb 15
N
N/2
0
0
N/2
Number of bit transitions
ELEC 7770: Advanced VLSI Design (Agrawal)
N
16
Sent data
Received data
Bus-Inversion Encoding Logic
Polarity
decision
logic
Spring 07, Feb 15
Bus register
Polarity bit
M. Stan and W. Burleson, “Bus-Invert
Coding for Low Power I/O,” IEEE Trans.
VLSI Systems, vol. 3, no. 1, pp. 49-58,
March 1995.
ELEC 7770: Advanced VLSI Design (Agrawal)
17
Clock-Gating in Low-Power Flip-Flop
D
D
Q
CK
Spring 07, Feb 15
ELEC 7770: Advanced VLSI Design (Agrawal)
18
Reduced-Power Shift Register
D
Q
D
Q
D
Q
D
Q
multiplexer
D
D
Q
D
Q
D
Q
D
Output
Q
CK(f/2)
Flip-flops are operated at full voltage and half the clock frequency.
Spring 07, Feb 15
ELEC 7770: Advanced VLSI Design (Agrawal)
19
Power Consumption of Shift Register
16-bit shift register, 2μ CMOS
Freq
(MHz)
Power
(μW)
1
33.0
1535
2
16.5
887
4
8.25
738
C. Piguet, “Circuit and Logic Level
Design,” pages 103-133 in W. Nebel
and J. Mermet (ed.), Low Power
Design in Deep Submicron
Electronics, Springer, 1997.
Spring 07, Feb 15
1.0
Normalized power
Deg. Of
parallelism
P = C’VDD2f/n
0.5
0.25
0.0
1
2
4
Degree of parallelism, n
ELEC 7770: Advanced VLSI Design (Agrawal)
20