Transcript Lecture 12: Pass Transistor Logic: A Low Power Logic Family

ELEC 5270/6270 Spring 2011
Low-Power Design of Electronic Circuits
Pass Transistor Logic: A Low Power
Logic Family
Vishwani D. Agrawal
James J. Danaher Professor
Dept. of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr11/course.html
Copyright Agrawal, 2007
ELEC6270 Spring 11, Lecture 12
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Low-Power Logic Styles
Pass transistor logic
 Dynamic logic
 Domino logic
 Adiabatic and charge recovery logic
 Asynchronous logic
 Logic restructuring

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Pass Transistor Logic (PTL)

Requires fewer transistors
Smaller area
 Reduced capacitance
 Reduced energy and power

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CMOS AND Gate
A
F = AB
B
A
F = AB
B
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Pass Transistor AND Gate
B
A
F = AB
0
Need 4 transistors instead of 6 for CMOS AND gate.
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CMOS OR Gate
A
B
F =A+B
A
F =A+B
B
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Pass Transistor OR Gate
B
1
F =A+B
A
Need 4 transistors instead of 6 for CMOS OR gate.
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Reduced Voltage Swing
IN
Vx = VDD – Vtn
OUT
VDD = 2.5V
n transistors, W/L = 0.5μ/0.25μ
p transistors, W/L = 1.5μ/0.25μ
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Spice Simulation
3.0
Voltage, V
IN
2.0
Vx
1.0
OUT
0.0
0
0.5
1.0
1.5
2.0
Time, ns
J. M. Rabaey, A. Chandrakasan and B. Nokolić, Digital Integrated
Circuits, Upper Saddle River, New Jersey: Pearson Education, 2003.
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Voltage Transfer Characteristic
(VTC) of AND Gate
B
A
F = AB
0
n transistors, W/L = 0.5μ/0.25μ
p transistors, W/L = 1.5μ/0.25μ
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VTC: Spice Simulation
3.0
VDD – Vtn
F, V
2.0
B = VDD
A = 0 → VDD
1.0
0.0
A = VDD, B = 0 → VDD
A = B = 0 → VDD
0
0.5
1.0
1.5
2.0
2.5
Vin, V
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Energy If this voltage is insufficient
for turning the pMOS
Transistor in inverter off, leakage
power will be consumed.
0 → VDD
Vout
VDD = 2.5V
i(t)
E0→1
=
CL
T
∫ P(t) dt
0
T
= VDD ∫ i(t) dt
0
VDD-Vtn
= VDD ∫ CL dVout
0
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= CL VDD (VDD – Vtn) < CL VDD2
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Energy: PTL vs. CMOS
PTL consumes less dynamic power than
static CMOS Logic.
 PTL leakage may be higher when output is
low, because the reduced voltage level
may be insufficient to turn the PMOS
transistor in the inverter off.

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Ways to Reduce Leakage
Level restoration
 Multiple-threshold transistors
 Transmission-gate logic

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Level Restoration
VDD
Level
restorer
B=1
Vout
A=1
0
CL
Level restorer device should be weaker than the nMOS
pass transistor. Otherwise, VDD → 0 transition at Vout
will be impossible.
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Multiple-Threshold Transistors
Use zero-threshold pass-transistors.
 Use high-threshold transistors in all other
gates.
 This can cause leakage through multiple
gates.

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Leakage Through Zero-Threshold
Transistors
1
Zero or low-threshold
transistors
0
Leakage current path 0
1
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Transmission-Gate Logic
Provides both power and ground levels.
 Good design, except needs more transistors.

A
Inverting multiplexer
S’A’ + SB’
S
B
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Transmission-Gate XOR
B
AB’+A’B
A
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A Logic Library
Cell
Number of transistors
CMOS
OR02
6
MUX21
12
AND02
6
XOR2
12
AND03
8
AOI32
10
OAI21
6
OAI32
10
AO21
8
NOR04
8
OR03
8
NOR02_2x
4
OAI221
10
NAND02_2x
4
AOI321
12
INV02
2
DFFR
34
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TGL
6
6
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Synthesis of PTL
Shannon’s expansion:
Z
B
=
=
=
=
AB + BC + AC
A(B+BC+C) + A’(BC)
A(B+C) + A’BC
A[B+B’C] + A’[BC]
1
C
C
0
1
0
1
0
A
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1
0
Z
ELEC6270 Spring 11, Lecture 12
A
B
C
Z
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
0
1
0
1
1
1
1
0
1
1
1
1
1
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Pass-Transistor Cell
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Synthesis of Z = A’B + B’C + A’C’
A
0
B
C = 1, Z = A’B + B’
B = 1, Z = A’
B = 0, Z = 1
C = 0, Z = A’
C
Z
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Synthesis of Z = A’ + BC’ + B’C
C
C’
0
B
B’
A
A = 1, Z = BC’ + B’C
B = 1, Z = C’
B = 0, Z = C
A’
A = 0, Z = 1
Z
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Synthesis of Z = AB’C’ + A’B’C
C’
C
1
A = 1, Z = B’C’
B = 1, Z = 0
B = 0, Z = C’
A’
A
A = 0, Z = B’C
B = 1, Z = 0
B = 0, Z = C
B’
B
Z
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CPL: Complementary PassTransistor Logic
Every signal and its complement is
generated.
 Gates are static, because the output is
connected to either VDD or GND.
 Design is modular; same cell can produce
various gates by simply permuting the
input signals.
 Also called differential pass-transistor logic
(DPL)

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A CPL Cell
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CPL Cell Used As AND/NAND
B
B’
A
Z = AB
B
A’
Z’ = (AB)’
B’
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CPL Cell Used As OR/NOR
B’
B
A
Z =A+B
B
A’
Z’ = (A + B)’
B’
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CPL Cell Used As XOR/XNOR
B’
B
A
Z = AB’ + A’B
A’
A’
Z’ = AB + A’B’
A
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CPL vs. CMOS
CPL requires fewer transistors.
 Useful for modular (array) circuits like
adders, multipliers, barrel shifter, etc.
 CPL operation can be faster and energy
efficient.
 Following example is taken from:


M. E. Elrabaa, I. S. Abu-Khater, and M. I.
Elmasry, Advanced Low-Power Digital Circuit
Techniques, Springer, 1997, Chapter 2.
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Example: 4-Bit Carry Select Adder
A_1
B_1
Adder cell
A_2
B_2
Adder cell
A_3
B_3
Adder cell
A_4
B_4
Adder cell
S1’ S0’ C0’ C0 C1’ C1
S1’ S0’ C0’ C0 C1’ C1
S1’ S0’ C0’ C0 C1’ C1
S1’ S0’ C0’ C0 C1’ C1
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
C’_2
C’_0
C_0
M
S_1
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S_2
ELEC6270 Spring 11, Lecture 12
C’_4
S_3
S_4
C_4
32
CMOS Carry-Select Adder Cell
Ai
S1’
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Bi
S0’ C0’
C0
C1’
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C1
33
CPL Adder Cell
Ai
Bi
S1’
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S0’
C0’
C0
C1’
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C1
34
CPL Multiplexer Cell
in1
in2
M
Ci
Ci
out
Ci’
Ci’
in1
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in2
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32-Bit Adders in 0.8μ, 3.3V
Type of design
Type of logic
Energy
μW/MHz
Delay
ns
CMOS
90.0
11.0
CPL
65.0
10.0
CMOS
93.0
10.5
CPL
72.0
7.5
Minimum
transistor size
Transistor sizing
for delay
optimization
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References
G. R. Cho and T. Chen, “On the Impact of
Technology Scaling on Mixed PTL/Static
Logic,” Proc. IEEE Int. Conf. Computer
Design, 2002.
 R. Zimmermann and W. Fichtner, “LowPower Logic Styles: CMOS Versus PassTransistor Logic,” IEEE J. Solid State
Circuits, vol. 32, no. 7, pp. 1079-1090, July
1997.

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