Transcript Lecture 8: Adiabatic Logic

ELEC 5270/6270 Spring 2011
Low-Power Design of Electronic Circuits
Adiabatic Logic
Vishwani D. Agrawal
James J. Danaher Professor
Dept. of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr11/course.html
Copyright Agrawal, 2007
ELEC6270 Spring 11, Lecture 8
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Examples of Power Saving and
Energy Recovery

Power saving by power transmission at high
voltage:




1000W transmitted at 100V, current I = 10A
If resistance of transmission circuit is 1Ω, then power loss
= I2R = 100W
Transmit at 1000V, current I = 1A, transmission loss =
1W
Energy recovery from automobile braking:



Normal brake converts mechanical energy into heat
Instead, the energy can be stored in a flywheel, or
Converted to electricity to charge a battery
Copyright Agrawal, 2007
ELEC6270 Spring 11, Lecture 8
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Reexamine CMOS Gate
V2/ Rp
V
Most energy
dissipated here
i = Ve–t/RpC/Rp
v(t)
v(t)
p
Power
i2R
V×i = V2e–2t/RpC/ Rp
V
C
v(t)
3RpC
0
Energy dissipation per transition = Area/2 = C V 2/ 2
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ELEC6270 Spring 11, Lecture 8
Time, t
3
Charging with Constant Current
i = constant
v(t) = it/C
C
Power
i2Rp
C2V2R
0
Time (T) to charge capacitor to voltage V
v(T) = V = iT/C, or T = CV/i
Current, i = CV/T
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Output voltage, v(t)
V(t)
p
/T2
Time, t
it/C
V
0
T=CV/i
Power = i2Rp = C2V2Rp/T2
Energy dissipation
= Power × T = (RpC/T) CV2
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Or, Charge in Steps
0→V/2→V
i = Ve–t/RpC/2Rp
C
V2e–2t/RpC/4Rp
V2/4Rp
Power
v(t)
v(t)
i2Rp
0
Energy = Area = CV2/8
V
v(t)
V/2
3RpC
6RpC
Time, t
Total energy = CV2/8 + CV2/8 = CV2/4
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ELEC6270 Spring 11, Lecture 8
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Energy Dissipation of a Step
Voltage step = V/N
T
E = ∫ V2e–2t/RpC/(N2Rp) dt
0
= [CV2/(2N2)] (1 – e–2T/RpC)
≈ CV2/(2N2) for large T ≥ 3RpC
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ELEC6270 Spring 11, Lecture 8
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Charge in N Steps
Supply voltage 0 → V/N → 2V/N → 3V/N → . . . NV/N
Current, i(t)
= Ve–t/RpC/NRp
Power, i2(t)Rp
= V2e–2t/RpC/N2Rp
Energy = N CV2/2N2 = CV2/2N → 0 for N → ∞
Delay
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= N × 3RpC → ∞ for N → ∞
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Reexamine Charging of a Capacitor
R
t=0
v(t)
i(t)
C
V
Charge on capacitor, q(t)
=
C v(t)
Current, i(t)
=
C dv(t)/dt
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=
dq(t)/dt
ELEC6270 Spring 11, Lecture 8
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C dv(t)/dt =
[V – v(t)] /R
dv(t)
V – v(t)
───
=
─────
dt
RC
dv(t)
dt
∫ ───── = ∫ ────
V – v(t)
RC
–t
ln [V – v(t)]
=
── + A
RC
i(t)
=
Initial condition, t = 0, v(t) = 0 → A = ln V
–t
v(t) =
V [1 – exp(───)]
RC
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ELEC6270 Spring 11, Lecture 8
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v(t) =
i(t)
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=
–t
V [1 – exp( ── )]
RC
dv(t)
C ───
dt
=
ELEC6270 Spring 11, Lecture 8
V
–t
── exp( ── )
R
RC
10
Total Energy Per Charging
Transition from Power Supply
Etrans =
=
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∞
∫ V i(t) dt =
0
CV
∞V
2
–t
∫ ── exp( ── ) dt
0 R
RC
2
ELEC6270 Spring 11, Lecture 8
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Energy Dissipated per Transition in
Resistance
∞
V ∞
–2t
R ──
∫
exp(
──
)
dt
R2 0
RC
2
R ∫ i (t) dt=
2
0
=
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1
2
─ CV
2
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Energy Stored in Charged
Capacitor
∞
∞
–t V
–t
∫ v(t) i(t) dt = ∫ V [1– exp( ── )] ─ exp( ── ) dt
0
0
RC R
RC
1
2
= ─ CV
2
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ELEC6270 Spring 11, Lecture 8
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Slow Charging of a Capacitor
R
t=0
v(t)
i(t)
C
V(t)
Charge on capacitor, q(t)
=
C v(t)
Current, i(t)
=
C dv(t)/dt
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=
dq(t)/dt
ELEC6270 Spring 11, Lecture 8
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i(t)
=
[V(t) – v(t)] /R
C dv(t)/dt =
dv(t)
───
dt
=
V(t) – v(t)
─────
RC
dv(t)
dt
∫ ────── = ∫ ────
V(t) – v(t)
RC
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ELEC6270 Spring 11, Lecture 8
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Effects of Slow Charging
Voltage
Voltage across R
V(t)
v(t)
t
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ELEC6270 Spring 11, Lecture 8
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Constant Current Is Optimum
I(t)
R
t = [0,T]
V
C
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ELEC6270 Spring 11, Lecture 8
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Average and Instantaneous
Current
Let T be the time to charge C to voltage V
Average current:
(1/T)
Instantaneous current: I(t)
Where
Copyright Agrawal, 2007
T
∫ i(t) dt
0
T
∫ I(t) dt = I0
0
=
I0 + i(t)
=
0
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Energy Dissipation
E
=
=
=
=
=
Copyright Agrawal, 2007
T
T
R ∫ I2(t) dt= R ∫ [I0 + i(t)]2 dt
0
0
T
R ∫ [I02 + 2I0i(t) + i2(t)] dt
0
T
T
RI02T + 2RI0 ∫ i(t) dt + R ∫ i2(t) dt
0
0
T
RI02T + 0 + R ∫ i2(t) dt
≥ RI02T
0
RI02T, minimum value, when i(t) = 0, i.e., I(t) = I0
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Minimum Energy
For a constant current I0,
Charging time, T = CV/I0
Emin = RCVI0
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References


C. L. Seitz, A. H. Frey, S. Mattisson, S. D.
Rabin, D. A. Speck and J. L. A. van de
Snepscheut, “Hot-Clock nMOS,” Proc. Chapel
Hill Conf. VLSI, 1985, pp. 1-17.
W. C. Athas, L. J. Swensson, J. D. Koller, N.
Tzartzanis and E. Y.-C. Chou, “Low-Power
Digital Systems Based on Adiabatic-Switching
Principles,” IEEE Trans. VLSI Systems, vol. 2,
no. 4, pp. 398-407, Dec. 1994.
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ELEC6270 Spring 11, Lecture 8
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A Conventional Dynamic CMOS
Inverter
V
CK
P
E
P
E
P
E
CK
v(t)
vin
C
vin
v(t)
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ELEC6270 Spring 11, Lecture 8
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Adiabatic Dynamic CMOS Inverter
P
E
P
E
P
E
P
E
V
CK
0
v(t)
vin
Vf
+
C
vin
V-Vf
v(t)
0
CK
A. G. Dickinson and J. S. Denker, “Adiabatic Dynamic Logic,”
IEEE J. Solid-State Circuits, vol. 30, pp. 311-315, March 1995.
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ELEC6270 Spring 11, Lecture 8
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Cascaded Adiabatic Inverters
vin
CK1
CK2
CK1’
CK2’
input
CK1
precharge
evaluate
hold
CK2
CK1’
CK2’
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Complex ADL Gate
AB + C
A
C
Vf < Vth
B
CK
A. G. Dickinson and J. S. Denker, “Adiabatic Dynamic Logic,”
IEEE J. Solid-State Circuits, vol. 30, pp. 311-315, March 1995.
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ELEC6270 Spring 11, Lecture 8
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Clocks
EVAL.
HOLD
EVAL.
HOLD
VDD

0
VDD

0
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ELEC6270 Spring 11, Lecture 8
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Quasi-Adiabatic Logic Design
Possible Cases:
• The circuit output node X is LOW
and the pMOS tree is turned ON: X
follows  as it swings to HIGH
(EVALUATE phase)
• The circuit node X is LOW and the
nMOS tree is ON. X remains LOW
and no transition occurs (HOLD
phase)
• The circuit node X is HIGH and the
pMOS tree is ON. X remains HIGH
and no transition occurs (HOLD
phase)
• The circuit node X is HIGH and the
nMOS tree is ON. X follows  down
to LOW.
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A Case Study
K. Parameswaran, “Low Power Design of a 32-bit
Quasi-Adiabatic ARM Based Microprocessor,” Master’s Thesis,
Dept. of ECE, Rutgers University, New Brunswick, NJ, 2004.
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Quasi-Adiabatic 32-bit ARM Based
Microprocessor Design Specifications






Operating voltage: 2.5 V
Operating temperature: 25oC
Operating frequency: 10 MHz to 100 MHz
Leakage current: 0.5 fAmps
Load capacitance: 6X10-18 F (15% activity)
Transistor Count:
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ELEC6270 Spring 11, Lecture 8
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Technology Distribution

Microprocessor has a mix of static CMOS
and Quasi-adiabatic components
Quasi-Adiabatic
Static CMOS
Control Units
• ARM controller unit
• Bus control unit
ALU
• Adder-subtractor
unit
• Barrel shifter unit
• Booth-multiplier
unit
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Pipeline Units
• ID unit
• IF unit
• WB unit
• MEM unit
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Power Analysis
Datapath
Component
Power Consumption (mW)
Frequency 25 MHz
Power Consumption (mW)
Frequency 100 MHz
Quasiadiabatic
Static
CMOS
Power
Saved
Quasiadiabatic
Static
CMOS
Power
Saved
32-bit Adder
Subtracter
1.01
1.55
44%
1.29
1.62
20%
32-bit Barrel
Shifter
0.9
1.681
46%
1.368
1.8
24%
32-bit Booth
Multiplier
3.4
5.8
40%
5.15
6.2
17%
Power Consumption (mW)
Frequency 25 MHz
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Quasiadiabatic
Static
CMOS
Power
Saved
60 mW
85 mW
40%
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Power Analysis (Cont’d.)
Power Consumption Graph (25MHz)
6
5
Average Power 4
Consumption 3
(mW)
2
1
0
32-bit Adder- 32-bit Barrel 32-bit Booth
subtractor
shifter
multiplier
Datapath Component
Power Consumption Graph (100MHz)
Quasi-adiabatic
Static CMOS
7
6
5
Average Power
4
Consumption
3
(mW)
2
1
0
32-bit Adder- 32-bit Barrel
subtractor
shifter
32-bit Booth
multiplier
Datapath Component
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Area Analysis
Area (mm2)
Datapath
Component
Quasiadiabatic
Static CMOS
Area
Increase
32-bit Adder Subtracter
0.05
0.03
66%
32-bit Barrel Shifter
0.25
0.11
120%
32-bit Booth Multiplier
1.2
0.5
140%
Area Comparison Graph
Chip Area (mm2)
1.2
1
0.8
Area in mm2 0.6
Quasiadiabatic
Static
CMOS
Area
Increase
1.55
1.01
44%
0.4
0.2
0
32-bit Addersubtractor
32-bit Barrel
shifter
32-bit Booth
multiplier
Quasi-adiabatic
Static CMOS
Datapath Component
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ELEC6270 Spring 11, Lecture 8
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Summary

In principle, two types of adiabatic logic designs
have been proposed:

Fully-adiabatic




Adiabatic charging
Charge recovery: charge from a discharging capacitor is
used to charge the capacitance from the next stage.
W. C. Athas, L. J. Swensson, J. D. Koller, N. Tzartzanis and
E. Y.-C. Chou, “Low-Power Digital Systems Based on
Adiabatic-Switching Principles,” IEEE Trans. VLSI Systems,
vol. 2, no. 4, pp. 398-407, Dec. 1994.
Quasi-adiabatic


Adiabatic charging and discharging
Y. Ye and K. Roy, “QSERL: Quasi-Static Energy Recovery
Logic,” IEEE J. Solid-State Circuits, vol. 36, pp. 239-248,
Feb. 2001.
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