Lecture 13: Adiabatic Logic
Download
Report
Transcript Lecture 13: Adiabatic Logic
ELEC 5270/6270 Spring 2009
Low-Power Design of Electronic Circuits
Adiabatic Logic
Vishwani D. Agrawal
James J. Danaher Professor
Dept. of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr09/course.html
Copyright Agrawal, 2007
ELEC6270 Spring 09, Lecture 13
1
Examples of Power Saving and
Energy Recovery
Power saving by power transmission at high
voltage:
1000W transmitted at 100V, current I = 10A
If resistance of transmission circuit is 1Ω, then power loss
= I2R = 100W
Transmit at 1000V, current I = 1A, transmission loss =
1W
Energy recovery from automobile braking:
Normal brake converts mechanical energy into heat
Instead, the energy can be stored in a flywheel, or
Converted to electricity to charge a battery
Copyright Agrawal, 2007
ELEC6270 Spring 09, Lecture 13
2
Reexamine CMOS Gate
V2/ Rp
V
Most energy
dissipated here
i = Ve–t/RpC/Rp
v(t)
v(t)
p
Power
i2R
V×i = V2e–2t/RpC/ Rp
V
C
v(t)
3RpC
0
Energy dissipation per transition = Area/2 = C V 2/ 2
Copyright Agrawal, 2007
ELEC6270 Spring 09, Lecture 13
Time, t
3
Charging with Constant Current
i=K
v(t) = Kt/C
C
Power
i2Rp
C2V2R
0
Time (T) to charge capacitor to voltage V
v(T) = V = KT/C, or T = CV/K
Current, i = K = CV/T
Copyright Agrawal, 2007
p
/T2
Time, t
Kt/C
V
0
T=CV/K
Output voltage, v(t)
V(t)
Power = i2Rp = C2V2Rp/T2
Energy dissipation
= Power × T = (RpC/T) CV2
ELEC6270 Spring 09, Lecture 13
4
Or, Charge in Steps
0→V/2→V
i = Ve–t/RpC/2Rp
C
V2e–2t/RpC/4Rp
V2/4Rp
Power
v(t)
v(t)
i2Rp
0
Energy = Area = CV2/8
V
v(t)
V/2
3RpC
6RpC
Time, t
Total energy = CV2/8 + CV2/8 = CV2/4
Copyright Agrawal, 2007
ELEC6270 Spring 09, Lecture 13
5
Energy Dissipation of a Step
Voltage step = V/N
T
E = ∫ V2e–2t/RpC/(N2Rp) dt
0
= [CV2/(2N2)] (1 – e–2T/RpC)
≈ CV2/(2N2) for large T ≥ 3RpC
Copyright Agrawal, 2007
ELEC6270 Spring 09, Lecture 13
6
Charge in N Steps
Supply voltage 0 → V/N → 2V/N → 3V/N → . . . NV/N
Current, i(t)
= Ve–t/RpC/NRp
Power, i2(t)Rp
= V2e–2t/RpC/N2Rp
Energy = N CV2/2N2 = CV2/2N → 0 for N → ∞
Delay
Copyright Agrawal, 2007
= N × 3RpC → ∞ for N → ∞
ELEC6270 Spring 09, Lecture 13
7
Reexamine Charging of a Capacitor
R
t=0
v(t)
i(t)
C
V
Charge on capacitor, q(t)
=
C v(t)
Current, i(t)
=
C dv(t)/dt
Copyright Agrawal, 2007
=
dq(t)/dt
ELEC6270 Spring 09, Lecture 13
8
C dv(t)/dt =
[V – v(t)] /R
dv(t)
V – v(t)
───
=
─────
dt
RC
dv(t)
dt
∫ ───── = ∫ ────
V – v(t)
RC
–t
ln [V – v(t)]
=
── + A
RC
i(t)
=
Initial condition, t = 0, v(t) = 0 → A = ln V
–t
v(t) =
V [1 – exp(───)]
RC
Copyright Agrawal, 2007
ELEC6270 Spring 09, Lecture 13
9
v(t) =
i(t)
Copyright Agrawal, 2007
=
–t
V [1 – exp( ── )]
RC
dv(t)
C ───
dt
=
ELEC6270 Spring 09, Lecture 13
V
–t
── exp( ── )
R
RC
10
Total Energy Per Charging
Transition from Power Supply
Etrans =
=
Copyright Agrawal, 2007
∞
∫ V i(t) dt =
0
CV
∞V
2
–t
∫ ── exp( ── ) dt
0 R
RC
2
ELEC6270 Spring 09, Lecture 13
11
Energy Dissipated per Transition in
Resistance
∞
V ∞
–2t
R ──
∫
exp(
──
)
dt
R2 0
RC
2
R ∫ i (t) dt=
2
0
=
Copyright Agrawal, 2007
1
2
─ CV
2
ELEC6270 Spring 09, Lecture 13
12
Energy Stored in Charged
Capacitor
∞
∞
–t V
–t
∫ v(t) i(t) dt = ∫ V [1– exp( ── )] ─ exp( ── ) dt
0
0
RC R
RC
1
2
= ─ CV
2
Copyright Agrawal, 2007
ELEC6270 Spring 09, Lecture 13
13
Slow Charging of a Capacitor
R
t=0
v(t)
i(t)
C
V(t)
Charge on capacitor, q(t)
=
C v(t)
Current, i(t)
=
C dv(t)/dt
Copyright Agrawal, 2007
=
dq(t)/dt
ELEC6270 Spring 09, Lecture 13
14
i(t)
=
[V(t) – v(t)] /R
C dv(t)/dt =
dv(t)
───
dt
=
V(t) – v(t)
─────
RC
dv(t)
dt
∫ ────── = ∫ ────
V(t) – v(t)
RC
Copyright Agrawal, 2007
ELEC6270 Spring 09, Lecture 13
15
Effects of Slow Charging
Voltage
Voltage across R
V(t)
v(t)
t
Copyright Agrawal, 2007
ELEC6270 Spring 09, Lecture 13
16
References
C. L. Seitz, A. H. Frey, S. Mattisson, S. D.
Rabin, D. A. Speck and J. L. A. van de
Snepscheut, “Hot-Clock nMOS,” Proc. Chapel
Hill Conf. VLSI, 1985, pp. 1-17.
W. C. Athas, L. J. Swensson, J. D. Koller, N.
Tzartzanis and E. Y.-C. Chou, “Low-Power
Digital Systems Based on Adiabatic-Switching
Principles,” IEEE Trans. VLSI Systems, vol. 2,
no. 4, pp. 398-407, Dec. 1994.
Copyright Agrawal, 2007
ELEC6270 Spring 09, Lecture 13
17
A Conventional Dynamic CMOS
Inverter
V
CK
P
E
P
E
P
E
CK
v(t)
vin
C
vin
v(t)
Copyright Agrawal, 2007
ELEC6270 Spring 09, Lecture 13
18
Adiabatic Dynamic CMOS Inverter
P
E
P
E
P
E
P
E
V
CK
0
v(t)
vin
Vf
+
C
vin
V-Vf
v(t)
0
CK
A. G. Dickinson and J. S. Denker, “Adiabatic Dynamic Logic,”
IEEE J. Solid-State Circuits, vol. 30, pp. 311-315, March 1995.
Copyright Agrawal, 2007
ELEC6270 Spring 09, Lecture 13
19
Cascaded Adiabatic Inverters
vin
CK1
CK2
CK1’
CK2’
input
CK1
precharge
evaluate
hold
CK2
CK1’
CK2’
Copyright Agrawal, 2007
ELEC6270 Spring 09, Lecture 13
20
Complex ADL Gate
AB + C
A
C
Vf < Vth
B
CK
A. G. Dickinson and J. S. Denker, “Adiabatic Dynamic Logic,”
IEEE J. Solid-State Circuits, vol. 30, pp. 311-315, March 1995.
Copyright Agrawal, 2007
ELEC6270 Spring 09, Lecture 13
21
Quasi-Adiabatic Logic
Two
sets of diodes:
One controls the
charging path (D1)
while the other (D2)
controls the
discharging path
Supply lines have
EVALUATE phase
( swings up) and
HOLD phase (
swings up)
D1
Y. Ye and K. Roy, “QSERL: Quasi-Static Energy Recovery Logic,”
IEEE J. Solid-State Circuits, vol. 36, pp. 239-248, Feb. 2001.
Copyright Agrawal, 2007
ELEC6270 Spring 09, Lecture 13
22
Clocks
EVAL.
HOLD
EVAL.
HOLD
VDD
0
VDD
0
Copyright Agrawal, 2007
ELEC6270 Spring 09, Lecture 13
23
Quasi-Adiabatic Logic Design
Possible Cases:
• The circuit output node X is LOW
and the pMOS tree is turned ON: X
follows as it swings to HIGH
(EVALUATE phase)
• The circuit node X is LOW and the
nMOS tree is ON. X remains LOW
and no transition occurs (HOLD
phase)
• The circuit node X is HIGH and the
pMOS tree is ON. X remains HIGH
and no transition occurs (HOLD
phase)
• The circuit node X is HIGH and the
nMOS tree is ON. X follows down
to LOW.
Copyright Agrawal, 2007
ELEC6270 Spring 09, Lecture 13
24
A Case Study
K. Parameswaran, “Low Power Design of a 32-bit
Quasi-Adiabatic ARM Based Microprocessor,” Master’s Thesis,
Dept. of ECE, Rutgers University, New Brunswick, NJ, 2004.
Copyright Agrawal, 2007
ELEC6270 Spring 09, Lecture 13
25
Quasi-Adiabatic 32-bit ARM Based
Microprocessor Design Specifications
Operating voltage: 2.5 V
Operating temperature: 25oC
Operating frequency: 10 MHz to 100 MHz
Leakage current: 0.5 fAmps
Load capacitance: 6X10-18 F (15% activity)
Transistor Count:
Copyright Agrawal, 2007
ELEC6270 Spring 09, Lecture 13
26
Technology Distribution
Microprocessor has a mix of static CMOS
and Quasi-adiabatic components
Quasi-Adiabatic
Static CMOS
Control Units
• ARM controller unit
• Bus control unit
ALU
• Adder-subtractor
unit
• Barrel shifter unit
• Booth-multiplier
unit
Copyright Agrawal, 2007
Pipeline Units
• ID unit
• IF unit
• WB unit
• MEM unit
ELEC6270 Spring 09, Lecture 13
27
Power Analysis
Datapath
Component
Power Consumption (mW)
Frequency 25 MHz
Power Consumption (mW)
Frequency 100 MHz
Quasiadiabatic
Static
CMOS
Power
Saved
Quasiadiabatic
Static
CMOS
Power
Saved
32-bit Adder
Subtracter
1.01
1.55
44%
1.29
1.62
20%
32-bit Barrel
Shifter
0.9
1.681
46%
1.368
1.8
24%
32-bit Booth
Multiplier
3.4
5.8
40%
5.15
6.2
17%
Power Consumption (mW)
Frequency 25 MHz
Copyright Agrawal, 2007
Quasiadiabatic
Static
CMOS
Power
Saved
60 mW
85 mW
40%
ELEC6270 Spring 09, Lecture 13
28
Power Analysis (Cont’d.)
Power Consumption Graph (25MHz)
6
5
Average Power 4
Consumption 3
(mW)
2
1
0
32-bit Adder- 32-bit Barrel 32-bit Booth
subtractor
shifter
multiplier
Datapath Component
Power Consumption Graph (100MHz)
Quasi-adiabatic
Static CMOS
7
6
5
Average Power
4
Consumption
3
(mW)
2
1
0
32-bit Adder- 32-bit Barrel
subtractor
shifter
32-bit Booth
multiplier
Datapath Component
Copyright Agrawal, 2007
ELEC6270 Spring 09, Lecture 13
29
Area Analysis
Area (mm2)
Datapath
Component
Quasiadiabatic
Static CMOS
Area
Increase
32-bit Adder Subtracter
0.05
0.03
66%
32-bit Barrel Shifter
0.25
0.11
120%
32-bit Booth Multiplier
1.2
0.5
140%
Area Comparison Graph
Chip Area (mm2)
1.2
1
0.8
Area in mm2 0.6
Quasiadiabatic
Static
CMOS
Area
Increase
1.55
1.01
44%
0.4
0.2
0
32-bit Addersubtractor
32-bit Barrel
shifter
32-bit Booth
multiplier
Quasi-adiabatic
Static CMOS
Datapath Component
Copyright Agrawal, 2007
ELEC6270 Spring 09, Lecture 13
30
Summary
In principle, two types of adiabatic logic designs
have been proposed:
Fully-adiabatic
Adiabatic charging
Charge recovery: charge from a discharging capacitor is
used to charge the capacitance from the next stage.
W. C. Athas, L. J. Swensson, J. D. Koller, N. Tzartzanis and
E. Y.-C. Chou, “Low-Power Digital Systems Based on
Adiabatic-Switching Principles,” IEEE Trans. VLSI Systems,
vol. 2, no. 4, pp. 398-407, Dec. 1994.
Quasi-adiabatic
Adiabatic charging and discharging
Y. Ye and K. Roy, “QSERL: Quasi-Static Energy Recovery
Logic,” IEEE J. Solid-State Circuits, vol. 36, pp. 239-248,
Feb. 2001.
Copyright Agrawal, 2007
ELEC6270 Spring 09, Lecture 13
31