Transcript Lecture 5: Low Voltage Low-Power Devices

ELEC 5270/6270 Fall 2007
Low-Power Design of Electronic Circuits
Low Voltage Low-Power Devices
Vishwani D. Agrawal
James J. Danaher Professor
Dept. of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Fall07/course.html
Copyright Agrawal, 2007
ELEC6270 Fall 07, Lecture 5
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Capacitances
VDD
Source
C1
Drain
In
Out
Drain
C2
CW
Source
GND
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Miller Capacitance
VDD
C1
In
Out
CM
C2
CW
GND
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Before Transition
VDD
C1
In = 0
0 +VDD
CM
Out = VDD
C2
CW
GND
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After Transition
VDD
from pull-up
devices of
previous gate
+VDD
In
2
Energy from supply = 2 CM VDD
Effective capacitance = 2 CM
C1
0
Out
CM
C2
CW
GND
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Capacitances in MOSFET
Cgs
Cgd
Gate
Gate oxide
Source
Drain
Cg
Cs
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Bulk
Cd
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Bulk nMOSFET
Polysilicon
Gate
Drain
W
Source
n+
n+
L
p-type body (bulk)
SiO2
Thickness = tox
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Gate Capacitance
Cg
=
Cox WL = C0 , intrinsic cap.
Cg
=
Cpermicron W
Cpermicron =
where εox
εox
Cox L
=
── L
tox
= 3.9ε0 for Silicon dioxide
= 3.9×8.85×10-14 F/cm
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Approx. Intrinsic Capacitances
Region of operation
Capacitance
Cutoff
Linear
Saturation
Cgb
C0
0
0
Cgs
0
C0 /2
2/3 C0
Cgd
0
C0 /2
0
Cg =
Cgs+Cgd+Cgb
C0
C0
2/3 C0
Weste and Harris, CMOS VLSI Design, Addison-Wesley, 2005, p. 78.
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Low-Power Transistors
Device scaling to reduce capacitance and
voltage.
 Body bias to reduce threshold voltage and
leakage.
 Multiple threshold CMOS (MTCMOS).
 Silicon on insulator (SOI)

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Device Scaling

Reduced dimensions
Reduce supply voltage
 Reduce capacitances
 Reduce delay
 Increase leakage due to reduced VDD / Vth

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A Simplistic View

Assume:
 Dynamic
power dominates
 Power reduces as square of supply voltage; should
reduce with device scaling
 Power reduced linearly with capacitance; should
reduce with device scaling
 Delay is proportional to RC time constant; R is
constant with scaling, RC should reduce

Power reduces with scaling
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Simplistic View (Continued)

What if voltage is further reduced below the
constant electric field value?
 Will
power continue to reduce? Yes.
 Since RC is independent of voltage, can clock rate
remain unchanged?

Answer to last question:
 Yes,
if threshold voltage was zero.
 No, in reality. Because relatively higher threshold
voltage will delay the beginning of capacitor
charging/discharging.
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Consider Delay of Inverter
VDD
R
In
Out
C
tB
Charging of
C begins
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tB
GND
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Idealized Input and Output
tf
INPUT
VDD
Vth
0.5VDD
t B = t f Vth /VDD
OUTPUT
Gate delay
0.5VDD
tB
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0.69CR
ELEC6270 Fall 07, Lecture 5
time
15
Gate Delay
For VDD >Vth
Gate delay
=
(t fVth/VDD) + 0.69RC – 0.5 t
=
t f (Vth/VDD – 0.5 ) + 0.69RC
=
∞
f
For VDD ≤Vth
Gate delay
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Gate delay
Approx. Gate Delay vs. VDD
0.5t
f
0.69RC
0.5t
f
0
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1
2
VDD /Vth
3
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5
17
Power - Delay vs. VDD
0.5t
Power
Gate delay
~CVDD2
f
0.69RC
0.5t
With leakage
f
0
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1
2
VDD /Vth
3
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5
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Delay or
Energy-delay
product
Optimum Threshold Voltage
Vth = 0.7V Vth can be changed
by varying doping
Vth = 0.3V level, oxide
thickness and
body bias.
Delay
Energy-delay product
0
1
2
3
4
5
6
VDD / Vth
J. M. Rabaey and M. Pedram, Low Power Design Methodologies,
Boston, Springer, 1996, p. 26.
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Low-Voltage Inverter


Assumed always in saturation.
Modeled as ideal current source.
VDD
VDD
VDD
K(VDD+ Vthp)
Vi
Vo
CL
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Vi = 0
K(VDD+ Vthp)
Vo
K(VDD –Vthn)
ELEC6270 Fall 07, Lecture 5
CL
Vi =
VDD
K(VDD –Vthn)
Vo
CL
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Power Supply Scaling
Vth ≈ 0.35V
0.8
0.8
0.6
1.0
0.6
VDD= 0.5V
0.4
0.4
0.2
0.2
0.0
0.0
0.2
0.4
0.6
0.8
IDD mA
Vo Volts
1.0
VDD= 1V
0.0
1.0
Vi Volts
J. Segura and C. F. Hawkins, CMOS Electronics, How It Works,
How It Fails, IEEE Press and Wiley-Interscience, 2004, p. 116.
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Bulk nMOSFET
Polysilicon
Vgs
+
+ V
gd
+
Gate
Drain
Source
Vds
W
n+
n+
L
p-type body (bulk)
SiO2
Thickness = tox
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Transistor in Cut-Off State
------------------
Vg < 0
+
-
+++++++++++++
+++++++++++++
Polysilicon gate
SiO2
p-type body
+++++++++++++
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Threshold Voltage, Vth
+ + + + + + + + + +
0 < Vg < Vth
+
-
Depletion region
+++++++++++++
Polysilicon gate
SiO2
p-type body
+++++++++++++
Vth is a function of:
Dopant concentration,
Thickness of oxide
+++++++++++++
Vg > Vth
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+
-
------------------Depletion region
+++++++++++++
+++++++ ++++++
ELEC6270 Fall 07, Lecture 5
Polysilicon gate
SiO2
p-type body
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Cutoff: Ids = 0
Polysilicon
Vgs
+
+ V
gd
=0
+
Gate
Drain
Source
Vds = 0
W
n+
n+
L
p-type body (bulk)
SiO2
Thickness = tox
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Linear: Ids = 0
Polysilicon
Vgs
+
= Vgs
+ V
gd
> Vth
+
Gate
Drain
Source
n+
------
Vds = 0
W
n+
L
p-type body (bulk)
SiO2
Thickness = tox
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Linear: Ids Increases with Vds
Polysilicon
Vgs
+
> Vth
Gate
Vgs > Vgd > Vth
+ V
gd
+
0 < Vds < Vgs-Vth
Drain
Source
n+
-----L
W
n+
p-type body (bulk)
SiO2
Thickness = tox
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ELEC6270 Fall 07, Lecture 5
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Saturation: Ids Independent of Vds
Polysilicon
Vgs
+
Vgd < Vth
+ V
gd
+ 0 < Vds > Vgs- Vth
> Vth
Gate
Drain
Source
n+
-----L
W
n+
p-type body (bulk)
SiO2
Thickness = tox
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α-Power Law Model
Vgs > Vth and Vds > Vdsat = Vgs – Vth (Saturation region):
where
Ids
=
β
Pc ─ (Vgs – Vth)α
2
β
=
μCoxW/L,
μ = mobility
For fully ON transistor, Vgs = Vds = VDD:
Idsat
=
β
Pc ─ (VDD – Vth)α
2
T. Sakurai and A. R. Newton, “Alpha-Power Law MOSFET Model
and Its Applications to CMOS Inverter Delay and Other Formulas,”
IEEE J. Solid State Circuits, vol. 25, no. 2, pp. 584-594, 1990.
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α-Power Law Model (Cont.)
400
Shockley
Ids (μA)
300 α-power law
Simulation
Idsat
200
100
Vgs = 1.8V
0
0
0.3
0.6
0.9
1.2
1.5
1.8
Vds
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α-Power Law Model (Cont.)
Ids
Vdsat
=
=
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0
Vgs < Vth
cutoff
Idsat × Vds/Vdsat
Vds < Vdsat
linear
Idsat
Vds > Vdsat
saturation
Pv (Vgs – Vth)α/2
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α-Power Law Model (Cont.)

α = 2, for long channel devices or low VDD

α ~ 1, for short channel devices
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Power and Delay
Power
Inverter delay
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=
CVDD2
=
CVDD
1
1
──── (─── + ─── )
4
Idsatn Idsatp
=
KVDD
───────
(VDD – Vth)α
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Power-Delay Product
Power × Delay
=
VDD3
constant × ───────
(VDD – Vth)α
Power
Delay
0.6V
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1.8V
ELEC6270 Fall 07, Lecture 5
3.0V
VDD
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Optimum Threshold Voltage
For minimum power-delay product:
VDD
=
3Vth
───
3–α
For long channel devices, α = 2, VDD = 3Vth
For very short channel devices, α = 1, VDD = 1.5Vth
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Leakage
IG
Ground
VDD
R
n+
Isub
IPT
IGIDL
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ELEC6270 Fall 07, Lecture 5
n+
ID
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Leakage Current Components
Subthreshold conduction, Isub
 Reverse bias pn junction conduction, ID
 Gate induced drain leakage, IGIDL due to
tunneling at the gate-drain overlap
 Drain source punchthrough, IPT due to
short channel and high drain-source
voltage
 Gate tunneling, IG through thin oxide

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Subthreshold Leakage
Isub
Vgs – Vth
I0 exp( ───── ), where vT = kT/q = 26 mV
n vT
at 300K
=
Ids
Subthreshold
region
1mA
100μA
10μA
1μA
100nA
10nA
1nA
100pA
10pA
Vth
0
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Saturation region
0.3
0.6
0.9
1.2
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1.5
1.8 V
Vgs
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Normal CMOS Inverter
VDD
o
output
input
GND
SiO2
output
metal 1
GND
p+
Polysilicon (input)
n+
VDD
p+
n+
p+
n+
n-well
p-substrate (bulk)
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Leakage Reduction by Body Bias
VBBp
VDD
o
output
input
GND
VBBn
SiO2
VBBn GND
p+
n+
Polysilicon (input)
output
metal 1
VDD
VBBp
p+
n+
p+
n+
n-well
p-substrate (bulk)
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Body Bias, VBBn
+ + + + + + + + + +
0 < Vg < Vth
+
-
Depletion region
+++++++++++++
Polysilicon gate
SiO2
p-type body
+++++++++++++
Vt is a function of:
Dopant concentration,
Thickness of oxide
Vg < 0
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+
-
-----------------+++++++++++++
+++++++++++++
+++++++++++++
+++++++ ++++++
ELEC6270 Fall 07, Lecture 5
Polysilicon gate
SiO2
p-type body
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Further on Body Bias
Large body bias can increase gate
leakage (IG) via tunneling through oxide.
 Body bias is kept less than 0.5V.
 For VDD = 1.8V

 VBBn
= - 0.4V
 VBBp = 2.2V
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Summary

Device scaling down reduces supply
voltage
Reduced power
 Increases delay


Optimum power-delay product by scaling
down threshold voltage
 Threshold
voltage reduction increases
subthreshold leakage power


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Use body bias to reduce subthreshold leakage
Body bias may increase gate leakage
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