Transcript Lecture 13: Adiabatic Logic

ELEC 5270-001/6270-001(Fall 2006)
Low-Power Design of Electronic Circuits
Adiabatic Logic
Vishwani D. Agrawal
James J. Danaher Professor
Department of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
http://www.eng.auburn.edu/~vagrawal
[email protected]
Fall 2006: Dec. 5
ELEC 5270-001/6270-001 Lecture 13
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Examples of Power Saving and
Energy Recovery

Power saving by power transmission at high
voltage:
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1000W transmitted at 100V, current I = 10A
If resistance of transmission circuit is 1Ω, then power loss
= I2R = 100W
Transmit at 1000V, current I = 1A, transmission loss =
1W
Energy recovery from automobile brakes:



Normal brake converts mechanical energy into heat
Instead, the energy can be stored in a flywheel, or
Converted to electricity to charge a battery
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ELEC 5270-001/6270-001 Lecture 13
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Reexamine CMOS Gate
V2/Rp
V
Most energy
dissipated here
i = Ve-t/RpC/Rp
v(t)
v(t)
p
Power
i2R
VI = V2e-2t/RpC/Rp
V
C
v(t)
3RpC
0
Energy dissipation = Area/2 = CV2/2
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ELEC 5270-001/6270-001 Lecture 13
Time, t
3
Charging with Constant Current
i=K
v(t) = Kt/C
C
Power
i2Rp
C2V2R
p
/T2
0
Time (T) to charge capacitor to voltage V
v(T) = V = KT/C, or T = CV/K
Current, i = K = CV/T
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Output voltage, v(t)
V(t)
Time, t
Kt/C
V
0
t=CV/K
Power = i2Rp = C2V2Rp/T2
Energy dissipation
= Power × T = (RpC/T) CV2
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Or, Charge in Steps
0→V/2→V
i = Ve-t/RpC/2Rp
C
V2e-2t/RpC/4Rp
V2/4Rp
Power
v(t)
v(t)
i2Rp
0
Energy = Area = CV2/8
V
v(t)
V/2
3RpC
6RpC
Time, t
Total energy = CV2/8 + CV2/8 = CV2/4
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ELEC 5270-001/6270-001 Lecture 13
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Energy Dissipation of a Step
Voltage step = V/N
T
E = ∫ V2e-2t/RpC/(N2Rp) dt
0
= [CV2/(2N2)] (1 – e-2T/RpC)
≈ CV2/(2N2) for large T ≥ 3RpC
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Charge in N Steps
Supply voltage 0 → V/N → 2V/N → 3V/N → . . . NV/N
Current, i(t)
= Ve-t/RpC/NRp
Power, i2(t)Rp
= V2e-2t/RpC/N2Rp
Energy = N CV2/2N2 = CV2/2N → 0 for N → ∞
Delay
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= N × 3RpC → ∞ for N → ∞
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References


C. L. Seitz, A. H. Frey, S. Mattisson, S. D. Rabin,
D. A. Speck and J. L. A. van de Snepscheut,
“Hot-Clock nMOS,” Proc. Chapel Hill Conf. VLSI,
1985, pp. 1-17.
W. C. Athas, L. J. Swensson, J. D. Koller, N.
Tzartzanis and E. Y.-C. Chou, “Low-Power Digital
Systems Based on Adiabatic-Switching
Principles,” IEEE Trans. VLSI Systems, vol. 2, no.
4, pp. 398-407, Dec. 1994.
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A Conventional Dynamic CMOS
Inverter
V
CK
P
E
P
E
P
E
CK
v(t)
vin
C
vin
v(t)
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Adiabatic Dynamic CMOS Inverter
P
E
P
E
P
E
P
E
V
CK
0
v(t)
vin
Vf
+
C
vin
V-Vf
v(t)
0
CK
A. G. Dickinson and J. S. Denker, “Adiabatic Dynamic Logic,”
IEEE J. Solid-State Circuits, vol. 30, pp. 311-315, March 1995.
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Cascaded Adiabatic Inverters
vin
CK1
CK2
CK1’
CK2’
input
CK1
precharge
evaluate
hold
CK2
CK1’
CK2’
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Complex ADL Gate
AB + C
A
C
Vf < Vth
B
CK
A. G. Dickinson and J. S. Denker, “Adiabatic Dynamic Logic,”
IEEE J. Solid-State Circuits, vol. 30, pp. 311-315, March 1995.
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Quasi-Adiabatic Logic
Two sets of diodes:
One controls the
charging path (D1)
while the other (D2)
controls the
discharging path
 Supply lines have
EVALUATE phase (
swings up) and
HOLD phase (
swings low)

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D1
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Clocks
EVAL.
HOLD
EVAL.
HOLD
VDD

0
VDD

0
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Quasi-Adiabatic Logic Design
Possible Cases:
• The circuit output node X is LOW
and the pMOS tree is turned ON: X
follows  as it swings to HIGH
(EVALUATE phase)
• The circuit node X is LOW and the
nMOS tree is ON. X remains LOW
and no transition occurs (HOLD
phase)
• The circuit node X is HIGH and the
pMOS tree is ON. X remains HIGH
and no transition occurs (HOLD
phase)
• The circuit node X is HIGH and the
nMOS tree is ON. X follows  down
to LOW.
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A Case Study
K. Parameswaran, “Low Power Design of a 32-bit
Quasi-Adiabatic ARM Based Microprocessor,” Master’s Thesis,
Dept. of ECE, Rutgers University, New Brunswick, NJ, 2004.
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Quasi-Adiabatic 32-bit ARM Based
Microprocessor Design Specifications

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Operating voltage: 2.5 V
Operating temperature: 25oC
Operating frequency: 10 MHz to 100 MHz
Leakage current: 0.5 fAmps
Load capacitance: 6X10-18 F (15% activity)
Transistor Count:
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Technology Distribution

Microprocessor has a mix of static CMOS
and Quasi-adiabatic components
Quasi-Adiabatic
Static CMOS
Control Units
• ARM controller unit
• Bus control unit
ALU
• Adder-subtractor
unit
• Barrel shifter unit
• Booth-multiplier
unit
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Pipeline Units
• ID unit
• IF unit
• WB unit
• MEM unit
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Power Analysis
Datapath
Component
Power Consumption (mW)
Frequency 25 MHz
Power Consumption (mW)
Frequency 100 MHz
Quasiadiabatic
Static
CMOS
Power
Saved
Quasiadiabatic
Static
CMOS
Power
Saved
32-bit Adder
Subtracter
1.01
1.55
44%
1.29
1.62
20%
32-bit Barrel
Shifter
0.9
1.681
46%
1.368
1.8
24%
32-bit Booth
Multiplier
3.4
5.8
40%
5.15
6.2
17%
Power Consumption (mW)
Frequency 25 MHz
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Quasiadiabatic
Static
CMOS
Power
Saved
60 mW
85 mW
40%
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Power Analysis (Cont’d.)
Power Consumption Graph (25MHz)
6
5
Average Power 4
Consumption 3
(mW)
2
1
0
32-bit Adder- 32-bit Barrel 32-bit Booth
subtractor
shifter
multiplier
Datapath Component
Quasi-adiabatic
Static CMOS
Power Consumption Graph (100MHz)
7
6
5
Average Power
4
Consumption
3
(mW)
2
1
0
32-bit Adder- 32-bit Barrel
subtractor
shifter
32-bit Booth
multiplier
Datapath Component
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Area Analysis
Area (mm2)
Datapath
Component
Quasiadiabatic
Static CMOS
Area
Increase
32-bit Adder Subtracter
0.05
0.03
66%
32-bit Barrel Shifter
0.25
0.11
120%
32-bit Booth Multiplier
1.2
0.5
140%
Area Comparison Graph
Chip Area (mm2)
1.2
1
0.8
Quasiadiabatic
Static
CMOS
Area
Increase
1.55
1.01
44%
Area in mm2 0.6
0.4
0.2
0
32-bit Addersubtractor
32-bit Barrel
shifter
32-bit Booth
multiplier
Quasi-adiabatic
Static CMOS
Datapath Component
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Summary

In principle, two types of adiabatic logic designs
have been proposed:

Fully-adiabatic

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
Adiabatic charging
Charge recovery: charge from a discharging capacitor is used
to charge the capacitance from the next stage.
W. C. Athas, L. J. Swensson, J. D. Koller, N. Tzartzanis and E.
Y.-C. Chou, “Low-Power Digital Systems Based on AdiabaticSwitching Principles,” IEEE Trans. VLSI Systems, vol. 2, no. 4,
pp. 398-407, Dec. 1994.
Quasi-adiabatic


Adiabatic charging and discharging
Y. Ye and K. Roy, “QSERL: Quasi-Static Energy Recovery
Logic,” IEEE J. Solid-State Circuits, vol. 36, pp. 239-248, Feb.
2001.
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