Transcript Lecture 7: Dynamic Power: Glitch Elimination

ELEC 5270-001/6270-001(Fall 2006)
Low-Power Design of Electronic Circuits
Dynamic Power: Glitch Elimination
Vishwani D. Agrawal
James J. Danaher Professor
Department of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
http://www.eng.auburn.edu/~vagrawal
[email protected]
Fall 2006, Sep. 26, Oct. 3
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Components of Power

Dynamic

Signal transitions
Logic activity
 Glitches



Short-circuit
Static

Leakage
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Power of a Transition
isc
R
VDD
Dynamic Power
Vo
Vi
= CLVDD2/2 + Psc
CL
R
Ground
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Dynamic Power


Each transition of a gate consumes CV 2/2.
Methods of power saving:

Minimize load capacitances
Transistor sizing
 Library-based gate selection


Reduce transitions
Logic design
 Glitch reduction

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Glitch Power Reduction

Design a digital circuit for minimum
transient energy consumption by
eliminating hazards
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Theorem 1

For correct operation with minimum
energy consumption, a Boolean gate
must produce no more than one event
per transition.
Output logic state changes
One transition is necessary
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Output logic state unchanged
No transition is necessary
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Event Propagation
Single lumped inertial delay modeled for each gate
PI transitions assumed to occur without time skew
Path P1
1
0
13
P2
0
2
0
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1
3
2
246
Path P3
5
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Inertial Delay of an Inverter
Vin
dHL+dLH
d = ────
dHL
2
dLH
Vout
time
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Multi-Input Gate
A
Delay = d
C
B
A
DPD
B
C
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d
d Hazard or glitch
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Balanced Path Delays
A
DPD
Delay = d
C
B
A
B
C
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d No glitch
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Glitch Filtering by Inertia
A
Delay ≥ DPD
C
B
A
DPD
B
d =DPD
C
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Filtered glitch
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Theorem 2

Given that events occur at the input of a gate
with inertial delay d at times, t1 ≤ . . . ≤ tn , the
number of events at the gate output cannot
exceed
tn – t1
min ( n , 1 + -------d
)
tn - t1
t1
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t2
t3
tn
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time
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Minimum Transient Design

Minimum transient energy condition for a
Boolean gate:
| t i - tj | <
d
Where ti and tj are arrival times of input
events and d is the inertial delay of gate
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Balanced Delay Method



All input events arrive simultaneously
Overall circuit delay not increased
Delay buffers may have to be inserted
1
1
1
1
1
No increase in
critical path
delay
3
1
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1
1
1
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Hazard Filter Method



Gate delay is made greater than maximum input path
delay difference
No delay buffers needed (least transient energy)
Overall circuit delay may increase
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1
1
1
1
1
1
1
1
1
3
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Linear Program




Variables: gate and buffer delays
Objective: minimize number of buffers
Subject to: overall circuit delay
constraint for all input-output paths
Subject to: minimum transient condition
for all multi-input gates
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Variables for Full Adder add1b
0
0
0
0
0
1
1
1
0
0
1
0
0
0
1
1
1
0
0
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1
0
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Variables for Full Adder add1b


Gate delay variables d4 . . . d12
Buffer delay variables d15 . . . d29
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Objective Function

Ideal: minimize the number of non-zero delay
buffers (non-linear ILP):

Delay of ith buffer = xi di , where xi = [0, 1]
Minimize
Σ xi
buffers

An approximated LP:

Delay of ith buffer = di
Minimize
Σ di
buffers
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Specify Critical Path Delay
0
0
0
0
0
1
1
1
0
0
1
0
0
0
1
1
1
1
0
0
0
1
Sum of delays on critical path ≤ maxdel
maxdel = specified critical path delay
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Multi-Input Gate Condition
d1
0
0
0
d
1
d
1
0
0
1
0
1
|d1 - d2| ≤ d
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d
≡
d2
d1 - d2 ≤ d
d2 - d1 ≤ d
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Results: 1-Bit Adder
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AMPL Solution: maxdel = 6
1
2
1
1
1
2
1
1
1
2
2
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AMPL Solution: maxdel = 7
3
1
1
1
2
1
1
2
1
2
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AMPL Solution: maxdel ≥ 11
5
1
1
1
2
3
1
3
4
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Color codes for number of transitions
Original 1-Bit Adder
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Color codes for number of transitions
Optimized 1-Bit Adder
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Results: 1-Bit Adder
Simulated over all possible vector transitions
•Average power = optimized/unit delay
= 244 / 308 = 0.792
•Peak power
= optimized/unit delay
= 6 / 10 = 0.60
Power Savings :
Peak
= 40 %
Average = 21 %
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References




E. Jacobs and M. Berkelaar, “Using Gate Sizing to Reduce Glitch
Power,” Proc. ProRISC/IEEE Workshop on Circuits, Systems and
Signal Processing, Nov. 1996, pp. 183-188; also Int. Workshop
on Logic Synthesis, May 1997.
V. D. Agrawal, “Low-Power Design by Hazard Filtering,” Proc.
10th Int. Conf. VLSI Design, Jan. 1997, pp. 193-197.
V. D. Agrawal, M. L. Bushnell, G. Parthasarathy, and R.
Ramadoss, “Digital Circuit Design for Minimum Transient Energy
and a Linear Programming Method,” Proc. 12th Int. Conf. VLSI
Design, Jan. 1999, pp. 434-439.
Last two papers are available at website
http://www.eng.auburn.edu/~vagrawal
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A Limitation



Constraints are written by path enumeration.
Since number of paths in a circuit can be
exponential in circuit size, the formulation is
infeasible for large circuits.
Example: c880 has 6.96M constraints.
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Timing Window

Define two timing window variables per gate
output:

ti Earliest time of signal transition at gate i.

Ti Latest time of signal transition at gate i.
t1, T1
ti, Ti
.
.
.
i
tn, Tn
Ref: T. Raja, Master’s Thesis, Rutgers Univ., 2002
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Linear Program



Gate variables d4 . . . d12
Buffer Variables d15 . . . d29
Corresponding window variables t4 . . . t29 and T4 . .
. . T29.
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Multiple-Input Gate Constraints
For Gate 7:
T7 ≥ T5 + d7;
T7 ≥ T6 + d7;
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t7 < t5 + d7;
t7 < t6 + d7;
ELEC 5270-001/6270-001 Lecture 7
d7 > T7 - t7;
33
Single-Input Gate Constraints
Buffer 19:
T16 + d19 = T19 ;
t16 + d19 = t19 ;
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Overall Delay Constraints
T11 ≤ maxdelay
T12 ≤ maxdelay
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Number of constraints
Comparison of Constraints
Number of gates in circuit
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Estimation of Power




Circuit is simulated by an event-driven
simulator for both optimized and unoptimized gate delays.
All transitions at a gate are counted as
Events[gate].
Power consumed  Events[gate] x # of
fanouts.
Ref: “Effects of delay model on peak
power estimation of VLSI circuits,” Hsiao,
et al. (ICCAD`97 ).
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Results: 4-Bit ALU
maxdelay
Buffers inserted
7
10
12
15
5
2
1
0
Power Savings :
Peak = 33 %, Average = 21 %
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VDD
Open at t = 0
Large C
V
Circuit
Energy, E(t)
Power Calculation in Spice
Ground
t
1
1
2
E(t) = -- C VDD - -- C V 2 ~ C VDD ( VDD - V )
2
2
Ref.: M. Shoji, CMOS Digital Circuit Technology, Prentice Hall, 1988, p. 172.
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Power Dissipation of ALU4
Energy in nanojoules
7
1 micron CMOS, 57 gates, 14 PI, 8 PO
100 random vectors simulated in Spice
6
5
Original ALU
delay ~ 3.5ns
4
3
Minimum energy ALU
delay ~ 10ns
2
1
0
0.0
0.5
1.0
1.5
2.0
microseconds
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Signal Amplitude, Volts
F0 Output of ALU4
Original ALU, delay = 7 units (~3.5ns)
5
0
Minimum energy ALU, delay = 21 units (~10ns)
5
0
0
40
80
120
160
nanoseconds
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Benchmark Circuits
Circuit
Maxdel.
(gates)
No. of
Buffers
C432
17
34
95
66
0.72
0.62
0.67
0.60
C880
24
48
62
34
0.68
0.68
0.54
0.52
C6288
47
94
294
120
0.40
0.36
0.36
0.34
c7552
43
86
366
111
0.38
0.36
0.34
0.32
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Normalized Power
Average
Peak
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Physical Design
Gate
Gate
l/w
l/w
Gate
l/w
Gate
l/w
Gate delay modeled as a linear function of gate size, total load capacitance,
and fanout gate sizes (Berkelaar and Jacobs, 1996).
Layout circuit with some nominal gate sizes.
Enter extracted routing delays in LP as constants and solve for gate delays.
Change gate sizes as determined from a linear system of equations.
Iterate if routing delays change.
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Power Dissipation of ALU4
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References






R. Fourer, D. M. Gay and B. W. Kernighan, AMPL: A Modeling Language
for Mathematical Programming, South San Francisco: The Scientific
Press, 1993.
M. Berkelaar and E. Jacobs, “Using Gate Sizing to Reduce Glitch Power,”
Proc. ProRISC Workshop, Mierlo, The Netherlands, Nov. 1996, pp. 183188.
V. D. Agrawal, “Low Power Design by Hazard Filtering,” Proc. 10th Int’l
Conf. VLSI Design, Jan. 1997, pp. 193-197.
V. D. Agrawal, M. L. Bushnell, G. Parthasarathy and R. Ramadoss,
“Digital Circuit Design for Minimum Transient Energy and Linear
Programming Method,” Proc. 12th Int’l Conf. VLSI Design, Jan. 1999, pp.
434-439.
M. Hsiao, E. M. Rudnick and J. H. Patel, “Effects of Delay Model in Peak
Power Estimation of VLSI Circuits,” Proc. ICCAD, Nov. 1997, pp. 45-51.
T. Raja, A Reduced Constraint Set Linear Program for Low Power Design
of Digital Circuits, Master’s Thesis, Rutgers Univ., New Jersey, 2002.
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Conclusion

Glitch-free design through LP: constraint-set is linear in the size of the
circuit.

LP solution:

Eliminates glitches at all gate outputs,

Holds I/O delay within specification, and

Combines path-balancing and hazard-filtering to minimize the
number of delay buffers.

Linear constraint set LP produces results exactly identical to the LP
requiring exponential constraint-set.

Results show peak power savings up to 68% and average power savings
up to 64%.
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