Transcript Dacunha

11M
Neil D’Cunha
Everything about Asynchronus CPU's
- That you never cared about or ever wanted to know
• Name is a misnomer
o There are still sequential parts
o Just no global or circuit wide clocks
• Each module clocks the next module
o Self Timed or Self Clocked is a better name
o This is called a handshake protocol
My Handshake Protocol
• Initial attempt proved to be difficult to simulate
o Active Qn stage would clock Qn+1 stage
o Qn+1 would deactivate Qn
o Qn+1 would become Qn
• Problem: How to start this thing?
• Next attempt was to have a linear chain
o Each stage would clock the next stage
o Final stage would deactivate the next all stages
• Code proved to be unsynthesizeable
• Replaced with an FSM that replicated handshaking
Model of the my Asynchronous CPU
Operation
• Start (stage 0) is always forced high to simulate a valid
• Every state is in the "invalid" state
• Each stage
o Checks if previous stage is valid
o Does it's job
o Becomes valid
• Weird result - I created a 7 stage pipeline CPU
o Slight modifications to the code
 Control Registers
 Instruction Registers
My CPU in more detail
• Based off the PicoBlaze CPU for Xlinix FPGA's
o Tried to recreate similar functionality
o ALU has less functionality
• 16 Registers in Total
o 8 User Registers
o 8 System Registers - PC, RA, SP
• Most instructions can use a register or immediate value
• Very scalable - used parameterized VHDL code
Instruction Set Architecture
No Instruction Assembly
Machine Code
1
Addition
ADD $D $F $S
0000 $D [$F or O] [$S or O] M
2
Subtract
SUB $D $F $S
0001 $D [$F or O] [$S or O] M
3
AND
AND $D $F $S
0010 $D [$F or O] [$S or O] M
4
OR
OR $D $F $S
0011 $D [$F or O] [$S or O] M
5
Load Upper LUR $D HH M
0100 $D HH M
6
Load Lower LLR $D HH M
0101 $D HH M
7
Load Word
LM $D $F [$S or O] M
0110 $D $F [$S or O] M
8
Store Word
SM $D $F [$S or O] M
0111 $D $F [$S or O] M
9
Set Equal
SEQ $F [$S or O] M
1000 --- $F [$S or O] M
10 Set Unequal SNE $F [$S or O] M
1001 --- $F [$S or O] M
11 Set Lesser
1010 --- $F [$S or O] M
SLT $F [$S or O] M
12 Set Greater SGT $F [$S or O] M
1011 --- $F [$S or O] M
13 Input
INP $D [$S or O]
1100 $D --- [$S or O] M
14 Output
OUT $D [$F or O]
1100 --- $F [$S or O] M
15 Jump
JMP A [$F or OO] M
1110 A [$F or OO] M
16 Halt
HLT
1111 XXX XXX XXX XXX
Questions?