Transcript Beck

Pipeline Processor Design Project
Jarred Beck
Design Assumptions
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Three bit opcode
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This is to be able to address all of the 8k
memory directly. 213 = 8192
16 registers with some limitations
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In certain formats, only the first 8 are able to
reached
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Two reserved registers for the lw and sw.
Design Assumptions Cont.
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Pipeline Data Path Structure
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Ease of testability. (theoretically)
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Fast.
Compiler responsibility’s
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Hazard Prevention.
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Lw and Sw data moving.
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Jump return.
Register List
Register
$zero
$a0
$a1
$a2
$t0
$t1
$s0
$lr
$sr
$s0
$s1
$t2
$t3
$ra
Register #
0
1
2
3
4
5
6
7
8
9
10
11
12
13
Description
Holds constant zero value
Holds an argument value
Holds an argument value
Holds an argument value
Holds an argument value
Holds a temporary value
Holds a saved value
Last value loaded from memory
Last value stored into memory
Holds a saved value
Holds a saved value
Holds a saved value
Holds a saved value
Holds the return
Instruction Set
Instruction Set Formats
Inst. Type
Arithmatic (A)
Branch (Br)
Jump (J)
Memory (M)
Format
Opcode
Result Reg.
Argument 1
Argument
2
XXX
XXXX
XXXX
XXX
XX
Opcode
Compare
Reg. 1
Compare Reg.
2
Direction
Branch
Offset
XXX
XXX
XXX
X
XXXXXX
Opcode
Address
XXX
XXXXXXXXXXXXX
Opcode
Address
XXX
XXXXXXXXXXXXX
ALU Op
Instruction Set Cont.
Opcode Instructions
Arithmatic**
Jump (J)
Load Word (Lw)
Store Word (Sw)
Nop
Hlt
Beq
Bneq
** has sub opcodes
Instructions
Add
Sub
And
Or
Beq
Bneq
j
lw
sw
hlt
nop
Control Unit
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11 bits wide.
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Controls include
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Branch Flags
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Jump Flag
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Data Memory Read and Write Flags
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Register Write Flag
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Mux controls for Memory Input, Register Input,
and Register Address
Control Unit Cont.
Control Bit Function
10
Jump Flag
9
BEQ Flag
8
Data Read
7
Data Write
6
Data Select
Reg Write
5
Sel.
4
BNEQ Flag
3
Reg Write
2
PC Write
Branch
1
Signal
0
LW Addr Sel
Opcode
Instructions
Control
Pattern
Arithmatic**
00000001100
Jump (J)
10000000101
Load Word (Lw)
00100101100
Store Word (Sw)
00011000100
Nop
00000000100
Hlt
00000000000
Beq
01000000110
Bneq
00000010110
Datapath
Simulation Results
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Individual Components
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All Components passed tests
Datapath and CPU
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Datapath Passed tests
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Control Unit Passed test
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Memory passed
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Top level CPU problems
Moving Forward
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Debug Top level VHDL
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Altera passes compilation
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ModelSim gives error
Synthesize corrected version into board
Questions?
The End