Transcript Harley
CPU Design Project Christopher Brown Fall 2010, ELEC 5200 Overview Multi-cycle processor 16-bit instructions 16 registers Intel-style instruction set Registers AT - Assembler Temporary NULL - Readonly, always 0x0000 FULL - Readonly, always 0xFFFF R0 to R6 - General purpose, maintained across subroutines T0 to T3 - General purpose, not maintained across subroutines SP - Stack pointer, for use with pseudoinstructions such as push and pop IP - Instruction pointer, always points to the next instruction Dec Hex Name 0 0x0 AT 1 0x1 NULL 2 0x2 FULL 3 0x3 R0 4 0x4 R1 5 0x5 R2 6 0x6 R3 7 0x7 R4 8 0x8 R5 9 0x9 R6 10 0xA T0 11 0xB T1 12 0xC T2 13 0xD T3 14 0xE SP 15 0xF IP Instruction Set Jumps - JMP, JG, JNLE, JGE, JNL, JL, JNGE, JLE, JNG, JE, JNE Memory - MOV Arithmetic - ADD, SUB Bitwise - XOR, AND, OR Other - NOP, HLT Jumps 8-bit relative operand Flow determined by Sign, Ovrflw, and Zero control flags 11 varieties: Description JMP Jump JG JNLE 6 conditional 4 pseudo TRUE Jump if greater (>) Sign == Ovrflw && !Zero Jump if not less than or equal (not <=) Sign == Ovrflw && !Zero JGE Jump if greater than or equal (>=) Sign == Ovrflw JNL Jump if not less than (not <) Sign == Ovrflw Jump if less than (<) Sign != Ovrflw JL JNGE Jump if not greater or equal (not >=) 1 unconditional Condition Sign != Ovrflw Jump if less than or equal (<=) Sign != Ovrflw || Zero JNG Jump if not greater than (not >) Sign != Ovrflw || Zero JLE JE Jump if equal (==) JNE Jump if not equal (!=) Zero !Zero Memory Uses register indirect addressing only MOV (srcR), destR Loads the contents of memory at the address stored in srcR to the register specified by destR. MOV srcR, (destR) Stores the contents of srcR to the memory address stored in destR. Arithmetic ADD and SUB 2 variants of each ADD/SUB regR, destR Add or subtract the contents of regR from destR, storing the result in destR. ADD/SUB immed8, destR Add or subtract immed8 from destR, storing the result in destR. Updates Sign, Ovrflw, and Zero control flags. Bitwise XOR, AND, and OR XOR/AND/OR regR, destR Performs a binary operation between regR and destR, storing the result in destR. Updates Sign and Zero control flags. Other NOP It does nothing. HLT Puts the control unit into a halted state The only way to continue execution is through a reset Pseudo-Instructions PUSH regR SUB 1, SP MOV regR, (SP) POP regR MOV (SP), regR ADD 1, SP RET MOV (SP), IP ; POP IP ADD 1, SP CALL relM8XOR AT, ATADD IP, ATADD 4, ATSUB 1, SP ; PUSH ATMOV AT, (SP)JMP relM8 Data-Path Control Unit Finite-state-machine Moore machine - Outputs depend solely on the current state 8 unique states Also maintains 3 internal flags: Sign, Ovrflw, and Zero Control Unit Questions?