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CMOS邏輯元件
CD4008
-- ================================================================================
-- CD4008 4-Bit Binary Full Adder
--- Copyright (C),2013 Dr. C.H. Wei, STUST
--- This program is provided free of charge for educational purposes
--- Redistribution and use in binary form without modification, is permitted provided that the above copyright notice, this list of conditions
-- and the following disclaimer in the documentation and/or other materials provided with the distribution.
-- ================================================================================
CD4008.VHD
library
use
ieee;
ieee.std_logic_1164.all;
entity CD4008 is
port (
CI
A
B
CO
S
end entity CD4008;
:
:
:
:
:
in
in
in
out
out
std_logic;
std_logic_vector (3 downto 0);
std_logic_vector (3 downto 0);
std_logic;
std_logic_vector (3 downto 0));
CD4008.VHD
architecture dataflow of CD4008 is
signal
p
signal
g
signal
c1
signal
c2
signal
c3
begin
-- Create intermediate values
p <= A xor B;
g <= A and B;
: std_logic_vector (3 downto 0);
: std_logic_vector (3 downto 0);
: std_logic;
: std_logic;
: std_logic;
-- Do look ahead carry generation
c1 <= g(0) or (p(0) and C1);
c2 <= g(1) or (p(1) and c1);
c3 <= g(2) or (p(2) and c2);
CO <= g(3) or (p(3) and c3);
-- Perform the binary addition
S(0) <= '1' when (p(0) xor CI) = '1' else
'0' ;
S(1) <= '1' when (p(1) xor c1) = '1' else
'0' ;
S(2) <= '1' when (p(2) xor c2) = '1' else
'0' ;
S(3) <= '1' when (p(3) xor c3) = '1' else
'0' ;
end architecture;