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CMOS邏輯元件
CD4002
-- ================================================================================
-- CD4002 Dual 4-Input NOR Gates
--- Copyright (C),2013 Dr. C.H. Wei, STUST
--- This program is provided free of charge for educational purposes
--- Redistribution and use in binary form without modification, is permitted provided that the above copyright notice, this list of conditions
-- and the following disclaimer in the documentation and/or other materials provided with the distribution.
-- ================================================================================
CD4002.VHD
library
use
ieee;
ieee.std_logic_1164.all;
entity CD4002 is
port (
I2
I3
I4
I5
I9
I10
I11
I12
O1
O13
end entity CD4002;
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in
in
in
in
in
in
in
in
out
out
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic);
CD4002.VHD
architecture dataflow of CD4002 is
begin
O1 <= '1' when (I2 or I3 or I4 or I5) = '0' else
'0' ;
O13 <= '1' when (I9 or I10 or I11 or I12) = '0' else
'0' ;
end architecture;