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以光學鄰近修正為方法之奈米
級製程可製造性導向設計研究
進度報告
子計畫(一):適用於光學近區補償之整合環境設計
報告人:陳水和 賴冠妙
林立基
報告日期:2008/01/28
Schedule (1/2)
2007
Item
Object
OS
Language
Input
Output
2008
Sep Oct Nov Dec Jan Feb Mar Apr May
1
Mask
Partition
Linux
SKILL
<Virtuoso>
<db>
2
Sub-Mask
Partition
Linux
SKILL
<Virtuoso>
<db>
*
3
Conversion
from spo to
GDSII
Linux
<spo>
<db>
* *
4
Improvement of
the Feature
Sampling Point
Linux
Python
<dat>
<spi> <spo>
<txt> <tex>
5
EL Cross
Reference
Linux
Python
<dat>
<spi> <spo>
<txt> <tex>
6
EL Analysis
Report
Generator
Linux
Python
<dat>
<spi> <spo>
<txt> <tex>
7
MEF Cross
Reference
Linux
Python
<dat>
<spi> <spo>
<txt> <tex>
* * *
8
MEF Analysis
Report
Generator
Linux
Python
<dat>
<spi> <spo>
<txt> <tex>
*
*
Python
/ SKILL
* * *
* * *
*
Presenter: Shui-He Chen
Schedule (2/2)
2007
Item
Object
OS
Language
Input
Output
9
MEF of the 3
Sigma and
Mondecarlo
Linux
Python
<dat>
<spi> <spo>
<txt> <tex>
10
Process
Windows
Linux
Python
<dat>
<spi> <spo>
<txt> <tex>
11
Verification
Linux
Python
<dat>
<spi> <spo>
<txt> <tex>
12
Report
PC Window
Latex
<tex>
<pdf>
2008
Sep Oct Nov Dec Jan Feb Mar Apr May
* * *
* * *
* * * * * * *
* * * *
子計畫(一)一週進度報告
陳水和
1.To Modify the Program of Mask Error Factor Algorithm
by Using Python Language.
A Fast Lithography Verification Framework
for Litho-Friendly Layout Design
S. H. Choi, K. H. Lee, D. H. Kim, J. k. Hong, Y. H. Kim, M. H. Yoo,
and J. T. Kong
in Proceedings of the 6th International Symposium on Quality of
Electronic Design (ISQED), Jun 2005.
Advisor: Prof. Jing-Jou Tang
Presenter: Shui-He Chen
Outline




Introduction
Litho-Friendly Layout (LFL or LFD) Flow
Critical Area Extraction (CAE)
Full-Chip Level Layout Verification
‧Parameter Extraction and its Application
‧Mask Decomposition
‧Selective Simulation and its Application
‧Print-Image Based DRC and LVS

Summary and Conclusion
Introduction

This paper describe a critical area extraction
methodology in which a mask is pre-corrected
either by rule-or by model-based OPC and
propose a full-chip level photolithography
simulation method that can be used on mask data
verification
Litho-Friendly Layout Flow
VDD
A
B
A
X
B
VDD
Circuit Design
X
A
Litho-Friendly Layout Environment
A
B
Layout Design
Layout Modification
Rule/Model-Based
OPC
Rule/Model Optimization
Power/Ground Line
VDD
P-Type
N-Type
Gnd
Loosen
POLY
A
B
METAL
B
CONT
NWELL
Simulation-Based
CAE
Gnd
Enough
Process Margin
Rule-Based OPC
Model-Based OPC
FAITH Litho Simulation
VDD
NO
FAITH Litho Simulation
(Print-Image Based DRC & LVS)
A
B
Yes
Mask Data
Preparation
Mask Tape-Out
Gnd
Simulation-Based Critical Area
Extraction (CAE)
Parameter Extraction its Application
SCALAR
VECTOR
SEM
Weak
Point 1
Weak
Point 2
(a) Comparison of the Experimental CD and (b) Simulation Results on Sub-80nm Layout
Simulation CD
COST 
1  CDEXP  CDsim i 


N i
CDEXP

2
(1)
The simulation parameter extraction is to find the
optimum values to minimize the sum of differences
between the experimental CD and the simulation CD
as described in equation (1).
Mask Decomposition Method
λ is the optical system
wavelength.
NA is the numerical
aperture.
N
N
A mask is divided into
cell, N×N samples and
intensity for each cell is
(a) Whole Chip
computed separately.
For each sample mask,
the real simulation area is
extended by a critical
distance, 1.2λ/ NA to
eliminate the simulation
error due to the proximity
effect in figure (b).
Optical Interaction Range
(b) Mask Decomposition
Partially Coherent
Optical System
Patching
(d) Acceptable Area
(c)
CAE and the Selective Simulation
Acceptable Area
Simulation Area
5
4
1.2
Layout Pattern

NA
1
2
3
10μm
10μm
The hierarchical structure of the weak points
reduces the number of simulation cases.
Summary and Conclusion


For the full-chip level simulation, have applied the
automatic calibration of the simulation process
parameters, the mask decomposition method and
selective simulation method.
The 99.99% accuracy of global fitting has been achieved.
The end.
Thanks for your attention.
Rule-Based OPC
Virtual Edge Compensation Table
CD
(nm)
100
Spacing Length
(nm) (nm)
100
100
Rule
(nm)
0.04
110
110
110
0.03
120
120
120
0.025
Length
Spacing
CD
Pattern1
...
...
...
Spacing
Pattern2
Pattern3
...
The All Patterns are 1D Rule
Model-Based Flow
Pattern 1
Simulation
Compensation
Pattern 2
Pattern 3
Mask
No
Pattern 1
Pattern 1
Good Enough?
Yes
Pattern 2
Pattern 3
Pattern 2
Pattern 3
Mask
Mask
Example of CAE and its Verification
(a) Original Layout
(c) Simulation Result
(b) OPCed and ORC Result
(d) SEM Image
Optical Parameters Extraction and
Failure Observation
Intensity
Distance (nm)
(a) Exposure Latitude (EL)
(b) Depth of Focus (DOF)
% EL
Proper
% EL
DOF
Proper DOF
(c) Process
(d) Normalized Image Log-Slope (NILS)
Print-Image Based DRC/LVS
print-image
based LVS is
done to
compare the
original netlist
with a netlist
derived from
the print-image
layout.
(a) Original Layout
(b) Conventional DRC
(c) DRC of Recommended Rule
Schedule
2007
Item
Object
OS
Language
2008
Input Output Problem Sep Oct Nov Dec Jan Feb Mar Apr May
<spi spo
txt
tex py>
* *
1
MGUI
Linux
Python
2
SPLAT Parameter
Linux
Python
3
PLA Parameter
Linux
Python
<>
<>
* *
4
PSM Interface
Linux
Python
<>
<>
* *
5
OASIS Reader
Linux
Python
<oas>
<oas>
6
GDSII to OASIS
Linux
Python
<db>
<oas>
* *
7
Pattern Number
Reduction
Linux
Python
<db>
<spi>
* *
8
Mask Partition
Linux
Tcl
<db>
<db>
* *
9
Tcl GUI Interface
Linux
Tcl
<db>
<db>
*
<dat>
<spi>
* *
*
Presenter: Guan-Miao Lai
Schedule
2007
2008
Item
Object
OS
Language
Input Output Problem Sep Oct Nov Dec Jan Feb Mar Apr May
10
Dark Field &
Bright Field
Linux
Python
<dat>
<spi>
* *
11
Reverse Field
Partition
Linux
Python
<dat>
<spi>
* * *
Presenter: Guan-Miao Lai
子計畫(一)一週進度報告
Study Paper:
Efficient algorithms for polygon to trapezoid
decomposition and trapezoid corner stitching
Qiao Li and Sung-Mo Kang
Proceedings of the 10th Great Lakes symposium on VLSI , 2000, pp. 183-188.