Transcript lecture11_memory2.PPT

Chapter 5
Memory II
CSE 820
Equations
CPU execution time =
(CPU cycles + Memory-stall cycles) x clockCycleTime
Memory stall cycles = misses x penalty
= IC x miss/Inst x penalty
= IC x memAccess/Inst x missRate x penalty
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Hierarchy Questions
1. Block Placement
Where can a block be placed?
2. Block Identification
How is a block found?
3. Block Replacement
Which block should be replaced on a miss?
4. Write Strategy
What happens on a write?
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Cache Q1: Where to place?
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Cache Q2: How to find it?
block address
block offset
tag
•
•
•
•
index
Index selects the set
Tag checks all in the set
Offset selects within the block
Valid bit
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Cache Q3: Replacement?
• Random
– Simplest
• FIFO
• LRU
– Approximation
– Outperforms others for large caches
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Cache Q4: write?
• Reads are most common and easiest
• Writes
– Write through
– Write back
• On replacement
• Dirty bit
• Allocate?
– Write allocate
– No-write allocate
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Alpha 21264 Cache: Go through it on your own
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Equations
• Fig 5.9 has
12 memory performance equations
• Most are variations on
CPU = IC x CPI x cycles
AvgMemAccess = Hit + MissRate x MissPenalty
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AvgMemAccess = Hit + MissRate x MissPenalty
17 Cache Optimizations
• Reduce miss penalty
Multilevel, critical first, read-before-write, merging
writes, victim cache
• Reduce miss rate
Larger blocks and caches, higher associativity,
way prediction, compiler optimizations
• Reduce miss rate & penalty with parallelism
Non-blocking, hardware and software prefetch
• Reduce hit time
Size, translation, pipelined, trace
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Reducing Cache Miss Penalty
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Questions
• Why is a small cache fast?
• Why will a designer put L1 and L2
cache on a processor chip rather than
simply having a large L1 cache?
• Why is L1 direct mapped?
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Reducing Miss Penalty:
Multilevel Caches
• How does an L2 cache
reduce the miss penalty?
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Multilevel Cache
AvgMemAccessTime =
HitTimeL1 + MissRateL1 X MissPenaltyL1
where
MissPenaltyL1 =
HitTimeL2 + MissRateL2X MissPenaltyL2
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Terms
• Global miss rate = misses/CPUaccesses
– e.g. for L2 = MissRateL1 X MissRateL2
• Local miss rate = misses/CacheAccesses
– e.g. MissRateL2
measured on the leftovers from L1
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L1 vs L2 with 32K L1: small L2 is poor
What is good about this graph?
Hit time is good and so is avg memory latency.
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Inclusive vs Exclusive
• Inclusion: L1 is subset of L2
pro: consistency between I/O and cache (or
among multiprocessor caches) is easy—simply
check L2
e.g. P4
• Exclusive: L1 and L2 are disjoint
pro: useful when L2 is only slightly larger than L1
e.g. AMD Athlon
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Miss Penalty Reduction:
Critical Word First & Early Restart
• Critical word first: In multiword block,
bring in the desired word first.
• Early Restart: restart CPU when desired
word is received
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Miss Penalty Reduction:
Priority to Read
• Reads first
if no conflict with writes in write buffer
• Why?
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Miss Penalty Reduction:
Merging Write Buffer
• Within write buffer
merge words into blocks before writing
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Miss Penalty Reduction:
Victim Cache
• Remember last block discarded
• Algorithm:
on miss, if block is in victim cache, swap.
• Performance:
a 4-entry victim cache
can resolve ¼ of misses
• e.g. AMD Athlon (8 entries)
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Victim Cache
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Reducing Cache Miss Rate
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Miss Classification
• Compulsory:
first access cannot be in cache
• Capacity:
if cache cannot contain all blocks,
some accesses must miss
• Conflict: others
e.g. two blocks conflict by mapping to
same slot
(fully associative has no conflict)
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compulsory 
Capacity = fullyMichigan
associative
(decreases with size)
State University
Conflict
decreases
with
set size.
Computer
Science and
Engineering
Miss category as a percentage.
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